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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-31 13:03:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-31 13:03:03 -0700 |
| commit | eb08e71bd10004cb37c3ceab37607866d9240630 (patch) | |
| tree | 21754a7525d42c3662d081c7d9b995d731fae00f /techlibs | |
| parent | a379234f56753c3d72a6966c380ac6f83fde789c (diff) | |
| parent | ac2aff9e28a087a9a2697cd6ccf754af738903a7 (diff) | |
| download | yosys-eb08e71bd10004cb37c3ceab37607866d9240630.tar.gz yosys-eb08e71bd10004cb37c3ceab37607866d9240630.tar.bz2 yosys-eb08e71bd10004cb37c3ceab37607866d9240630.zip | |
Merge branch 'xaig' into xc7mux
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 2 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index c7c5ba168..b5e10fb20 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -149,7 +149,7 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) in always @(posedge C) Q <= D; `else - always @* Q = D; + always @* Q <= D; `endif endmodule diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ecfb94610..cc667b919 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -294,6 +294,7 @@ struct SynthXilinxPass : public ScriptPass else run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); run("clean"); + // This shregmap call infers fixed length shift registers after abc // has performed any necessary retiming if (!nosrl || help_mode) |