Merge remote-tracking branch 'origin/master' into xc7mux

5 files changed, 421 insertions, 230 deletions

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 8e43fe058..a424d3089 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1271,6 +1271,181 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$specify2 (EN, SRC, DST);
+
+parameter FULL = 0;
+parameter SRC_WIDTH = 1;
+parameter DST_WIDTH = 1;
+
+parameter SRC_DST_PEN = 0;
+parameter SRC_DST_POL = 0;
+
+parameter T_RISE_MIN = 0;
+parameter T_RISE_TYP = 0;
+parameter T_RISE_MAX = 0;
+
+parameter T_FALL_MIN = 0;
+parameter T_FALL_TYP = 0;
+parameter T_FALL_MAX = 0;
+
+input EN;
+input [SRC_WIDTH-1:0] SRC;
+input [DST_WIDTH-1:0] DST;
+
+localparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;
+
+`ifdef SIMLIB_SPECIFY
+specify
+	if (EN && SD==0 && !FULL) (SRC  => DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && SD==0 &&  FULL) (SRC  *> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && SD==1 &&  FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && SD==2 &&  FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+endspecify
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$specify3 (EN, SRC, DST, DAT);
+
+parameter FULL = 0;
+parameter SRC_WIDTH = 1;
+parameter DST_WIDTH = 1;
+
+parameter EDGE_EN = 0;
+parameter EDGE_POL = 0;
+
+parameter SRC_DST_PEN = 0;
+parameter SRC_DST_POL = 0;
+
+parameter DAT_DST_PEN = 0;
+parameter DAT_DST_POL = 0;
+
+parameter T_RISE_MIN = 0;
+parameter T_RISE_TYP = 0;
+parameter T_RISE_MAX = 0;
+
+parameter T_FALL_MIN = 0;
+parameter T_FALL_TYP = 0;
+parameter T_FALL_MAX = 0;
+
+input EN;
+input [SRC_WIDTH-1:0] SRC;
+input [DST_WIDTH-1:0] DST, DAT;
+
+localparam ED = EDGE_EN     ? (EDGE_POL    ? 1 : 2) : 0;
+localparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;
+localparam DD = DAT_DST_PEN ? (DAT_DST_POL ? 1 : 2) : 0;
+
+`ifdef SIMLIB_SPECIFY
+specify
+	// DD=0
+
+	if (EN && DD==0 && SD==0 && ED==0 && !FULL) (        SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+	if (EN && DD==0 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+	if (EN && DD==0 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==0 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST  : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+	// DD=1
+
+	if (EN && DD==1 && SD==0 && ED==0 && !FULL) (        SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+	if (EN && DD==1 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+	if (EN && DD==1 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==1 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+	// DD=2
+
+	if (EN && DD==2 && SD==0 && ED==0 && !FULL) (        SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==0 && ED==0 &&  FULL) (        SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==0 && ED==1 &&  FULL) (posedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC  => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==0 && ED==2 &&  FULL) (negedge SRC  *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+	if (EN && DD==2 && SD==1 && ED==0 && !FULL) (        SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==1 && ED==0 &&  FULL) (        SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==1 && ED==1 &&  FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==1 && ED==2 &&  FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+	if (EN && DD==2 && SD==2 && ED==0 && !FULL) (        SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==2 && ED==0 &&  FULL) (        SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==2 && ED==1 &&  FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+	if (EN && DD==2 && SD==2 && ED==2 &&  FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+endspecify
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$specrule (EN_SRC, EN_DST, SRC, DST);
+
+parameter TYPE = "";
+parameter T_LIMIT = 0;
+parameter T_LIMIT2 = 0;
+
+parameter SRC_WIDTH = 1;
+parameter DST_WIDTH = 1;
+
+parameter SRC_PEN = 0;
+parameter SRC_POL = 0;
+
+parameter DST_PEN = 0;
+parameter DST_POL = 0;
+
+input EN_SRC, EN_DST;
+input [SRC_WIDTH-1:0] SRC;
+input [DST_WIDTH-1:0] DST;
+
+`ifdef SIMLIB_SPECIFY
+specify
+	// TBD
+endspecify
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$assert (A, EN);
 
 input A, EN;
@@ -1863,4 +2038,5 @@ end
 endmodule
 
 `endif
+
 // --------------------------------------------------------
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 40e54f9f0..c7c5ba168 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -957,10 +957,21 @@ endmodule
 
 (* blackbox *)
 module SB_HFOSC(
+	input TRIM0,
+	input TRIM1,
+	input TRIM2,
+	input TRIM3,
+	input TRIM4,
+	input TRIM5,
+	input TRIM6,
+	input TRIM7,
+	input TRIM8,
+	input TRIM9,
 	input CLKHFPU,
 	input CLKHFEN,
 	output CLKHF
 );
+parameter TRIM_EN = "0b0";
 parameter CLKHF_DIV = "0b00";
 endmodule
 
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index d2291b8d4..639cba2c2 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -17,254 +17,243 @@
  *
  */
 
-#include "kernel/register.h"
 #include "kernel/celltypes.h"
-#include "kernel/rtlil.h"
 #include "kernel/log.h"
+#include "kernel/register.h"
+#include "kernel/rtlil.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
 struct SynthIntelPass : public ScriptPass {
-  SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { }
+	SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") {}
 
-  void help() YS_OVERRIDE
-  {
-    //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-    log("\n");
-    log("    synth_intel [options]\n");
-    log("\n");
-    log("This command runs synthesis for Intel FPGAs.\n");
-    log("\n");
-    log("    -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n");
-    log("        generate the synthesis netlist for the specified family.\n");
-    log("        MAX10 is the default target if no family argument specified.\n");
-    log("        For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
-    log("        Cyclone V and Arria 10 GX devices are experimental, use it with a10gx argument.\n");
-    log("\n");
-    log("    -top <module>\n");
-    log("        use the specified module as top module (default='top')\n");
-    log("\n");
-    log("    -vqm <file>\n");
-    log("        write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
-    log("        output file is omitted if this parameter is not specified.\n");
-    log("\n");
-    log("    -vpr <file>\n");
-    log("        write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n");
-    log("        compatible with the Quartus flow. Writing of an\n");
-    log("        output file is omitted if this parameter is not specified.\n");
-    log("\n");
-    log("    -run <from_label>:<to_label>\n");
-    log("        only run the commands between the labels (see below). an empty\n");
-    log("        from label is synonymous to 'begin', and empty to label is\n");
-    log("        synonymous to the end of the command list.\n");
-    log("\n");
-    log("    -noiopads\n");
-    log("        do not use altsyncram cells in output netlist\n");
-    log("\n");
-    log("    -nobram\n");
-    log("        do not use altsyncram cells in output netlist\n");
-    log("\n");
-    log("    -noflatten\n");
-    log("        do not flatten design before synthesis\n");
-    log("\n");
-    log("    -retime\n");
-    log("        run 'abc' with -dff option\n");
-    log("\n");
-    log("The following commands are executed by this synthesis command:\n");
-    help_script();
-    log("\n");
-  }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    synth_intel [options]\n");
+		log("\n");
+		log("This command runs synthesis for Intel FPGAs.\n");
+		log("\n");
+		log("    -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n");
+		log("        generate the synthesis netlist for the specified family.\n");
+		log("        MAX10 is the default target if not family argument specified.\n");
+		log("        For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
+		log("        Cyclone V and Arria 10 GX devices are experimental, use it with a10gx argument.\n");
+		log("\n");
+		log("    -top <module>\n");
+		log("        use the specified module as top module (default='top')\n");
+		log("\n");
+		log("    -vqm <file>\n");
+		log("        write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
+		log("        output file is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -vpr <file>\n");
+		log("        write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n");
+		log("        compatible with the Quartus flow. Writing of an\n");
+		log("        output file is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -run <from_label>:<to_label>\n");
+		log("        only run the commands between the labels (see below). an empty\n");
+		log("        from label is synonymous to 'begin', and empty to label is\n");
+		log("        synonymous to the end of the command list.\n");
+		log("\n");
+		log("    -noiopads\n");
+		log("        do not use altsyncram cells in output netlist\n");
+		log("\n");
+		log("    -nobram\n");
+		log("        do not use altsyncram cells in output netlist\n");
+		log("\n");
+		log("    -noflatten\n");
+		log("        do not flatten design before synthesis\n");
+		log("\n");
+		log("    -retime\n");
+		log("        run 'abc' with -dff option\n");
+		log("\n");
+		log("The following commands are executed by this synthesis command:\n");
+		help_script();
+		log("\n");
+	}
 
-  string top_opt, family_opt, vout_file, blif_file;
-  bool retime, flatten, nobram, noiopads;
+	string top_opt, family_opt, vout_file, blif_file;
+	bool retime, flatten, nobram, noiopads;
 
-  void clear_flags() YS_OVERRIDE
-  {
-    top_opt = "-auto-top";
-    family_opt = "max10";
-    vout_file = "";
-    blif_file = "";
-    retime = false;
-    flatten = true;
-    nobram = false;
-    noiopads = false;
-  }
+	void clear_flags() YS_OVERRIDE
+	{
+		top_opt = "-auto-top";
+		family_opt = "max10";
+		vout_file = "";
+		blif_file = "";
+		retime = false;
+		flatten = true;
+		nobram = false;
+		noiopads = false;
+	}
 
-  void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
-  {
-    string run_from, run_to;
-    clear_flags();
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		string run_from, run_to;
+		clear_flags();
 
-    size_t argidx;
-    for (argidx = 1; argidx < args.size(); argidx++)
-      {
-        if (args[argidx] == "-family" && argidx+1 < args.size()) {
-          family_opt = args[++argidx];
-          continue;
-        }
-        if (args[argidx] == "-top" && argidx+1 < args.size()) {
-          top_opt = "-top " + args[++argidx];
-          continue;
-        }
-        if (args[argidx] == "-vqm" && argidx+1 < args.size()) {
-          vout_file = args[++argidx];
-          continue;
-        }
-        if (args[argidx] == "-vpr" && argidx+1 < args.size()) {
-          blif_file = args[++argidx];
-          continue;
-        }
-        if (args[argidx] == "-run" && argidx+1 < args.size()) {
-          size_t pos = args[argidx+1].find(':');
-          if (pos == std::string::npos)
-            break;
-          run_from = args[++argidx].substr(0, pos);
-          run_to = args[argidx].substr(pos+1);
-          continue;
-        }
-        if (args[argidx] == "-noiopads") {
-          noiopads = true;
-          continue;
-        }
-        if (args[argidx] == "-nobram") {
-          nobram = true;
-          continue;
-        }
-        if (args[argidx] == "-noflatten") {
-          flatten = false;
-          continue;
-        }
-        if (args[argidx] == "-retime") {
-          retime = true;
-          continue;
-        }
-        break;
-      }
-    extra_args(args, argidx, design);
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-family" && argidx + 1 < args.size()) {
+				family_opt = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-top" && argidx + 1 < args.size()) {
+				top_opt = "-top " + args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-vqm" && argidx + 1 < args.size()) {
+				vout_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-vpr" && argidx + 1 < args.size()) {
+				blif_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-run" && argidx + 1 < args.size()) {
+				size_t pos = args[argidx + 1].find(':');
+				if (pos == std::string::npos)
+					break;
+				run_from = args[++argidx].substr(0, pos);
+				run_to = args[argidx].substr(pos + 1);
+				continue;
+			}
+			if (args[argidx] == "-noiopads") {
+				noiopads = true;
+				continue;
+			}
+			if (args[argidx] == "-nobram") {
+				nobram = true;
+				continue;
+			}
+			if (args[argidx] == "-noflatten") {
+				flatten = false;
+				continue;
+			}
+			if (args[argidx] == "-retime") {
+				retime = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
 
-    if (!design->full_selection())
-      log_cmd_error("This command only operates on fully selected designs!\n");
-    if (family_opt != "max10" && family_opt !="a10gx" && family_opt != "cyclonev" && family_opt !="cycloneiv" && family_opt !="cycloneive" && family_opt != "cyclone10")
-      log_cmd_error("Invalid or no family specified: '%s'\n", family_opt.c_str());
+		if (!design->full_selection())
+			log_cmd_error("This command only operates on fully selected designs!\n");
+		if (family_opt != "max10" && family_opt != "a10gx" && family_opt != "cyclonev" && family_opt != "cycloneiv" &&
+		    family_opt != "cycloneive" && family_opt != "cyclone10")
+			log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
 
-    log_header(design, "Executing SYNTH_INTEL pass.\n");
-    log_push();
+		log_header(design, "Executing SYNTH_INTEL pass.\n");
+		log_push();
 
-    run_script(design, run_from, run_to);
+		run_script(design, run_from, run_to);
 
-    log_pop();
-  }
+		log_pop();
+	}
 
-  void script() YS_OVERRIDE
-  {
-    if (check_label("begin"))
-      {
-        if(check_label("family") && family_opt=="max10")
-          run("read_verilog -sv -lib +/intel/max10/cells_sim.v");
-        else if(check_label("family") && family_opt=="a10gx")
-          run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v");
-        else if(check_label("family") && family_opt=="cyclonev")
-          run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v");
-        else if(check_label("family") && family_opt=="cyclone10")
-          run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v");
-        else if(check_label("family") && family_opt=="cycloneiv")
-          run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
-        else
-          run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v");
-        // Misc and common cells
-        run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
-        run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
-        run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
-      }
+	void script() YS_OVERRIDE
+	{
+		if (check_label("begin")) {
+			if (check_label("family") && family_opt == "max10")
+				run("read_verilog -sv -lib +/intel/max10/cells_sim.v");
+			else if (check_label("family") && family_opt == "a10gx")
+				run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v");
+			else if (check_label("family") && family_opt == "cyclonev")
+				run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v");
+			else if (check_label("family") && family_opt == "cyclone10")
+				run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v");
+			else if (check_label("family") && family_opt == "cycloneiv")
+				run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
+			else
+				run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v");
+			// Misc and common cells
+			run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
+			run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
+			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+		}
 
-    if (flatten && check_label("flatten", "(unless -noflatten)"))
-      {
-        run("proc");
-        run("flatten");
-        run("tribuf -logic");
-        run("deminout");
-      }
+		if (flatten && check_label("flatten", "(unless -noflatten)")) {
+			run("proc");
+			run("flatten");
+			run("tribuf -logic");
+			run("deminout");
+		}
 
-    if (check_label("coarse"))
-      {
-        run("synth -run coarse");
-      }
+		if (check_label("coarse")) {
+			run("synth -run coarse");
+		}
 
-    if (!nobram && check_label("bram", "(skip if -nobram)"))
-      {
-        run("memory_bram -rules +/intel/common/brams.txt");
-        run("techmap -map +/intel/common/brams_map.v");
-      }
+		if (!nobram && check_label("bram", "(skip if -nobram)")) {
+			run("memory_bram -rules +/intel/common/brams.txt");
+			run("techmap -map +/intel/common/brams_map.v");
+		}
 
-    if (check_label("fine"))
-      {
-        run("opt -fast -mux_undef -undriven -fine -full");
-        run("memory_map");
-        run("opt -undriven -fine");
-        run("dffsr2dff");
-        run("dff2dffe -direct-match $_DFF_*");
-        run("opt -fine");
-        run("techmap -map +/techmap.v");
-        run("opt -full");
-        run("clean -purge");
-        run("setundef -undriven -zero");
-        if (retime || help_mode)
-          run("abc -markgroups -dff", "(only if -retime)");
-      }
+		if (check_label("fine")) {
+			run("opt -fast -mux_undef -undriven -fine -full");
+			run("memory_map");
+			run("opt -undriven -fine");
+			run("dffsr2dff");
+			run("dff2dffe -direct-match $_DFF_*");
+			run("opt -fine");
+			run("techmap -map +/techmap.v");
+			run("opt -full");
+			run("clean -purge");
+			run("setundef -undriven -zero");
+			if (retime || help_mode)
+				run("abc -markgroups -dff", "(only if -retime)");
+		}
 
-    if (check_label("map_luts"))
-      {
-        if(family_opt=="a10gx" || family_opt=="cyclonev")
-          run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
-        else
-          run("abc -lut 4" + string(retime ? " -dff" : ""));
-        run("clean");
-      }
+		if (check_label("map_luts")) {
+			if (family_opt == "a10gx" || family_opt == "cyclonev")
+				run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
+			else
+				run("abc -lut 4" + string(retime ? " -dff" : ""));
+			run("clean");
+		}
 
-    if (check_label("map_cells"))
-      {
-        if (!noiopads)
-          run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
-        if(family_opt=="max10")
-          run("techmap -map +/intel/max10/cells_map.v");
-        else if(family_opt=="a10gx")
-          run("techmap -map +/intel/a10gx/cells_map.v");
-        else if(family_opt=="cyclonev")
-          run("techmap -map +/intel/cyclonev/cells_map.v");
-        else if(family_opt=="cyclone10")
-          run("techmap -map +/intel/cyclone10/cells_map.v");
-        else if(family_opt=="cycloneiv")
-          run("techmap -map +/intel/cycloneiv/cells_map.v");
-        else
-          run("techmap -map +/intel/cycloneive/cells_map.v");
-        run("dffinit -highlow -ff dffeas q power_up");
-        run("clean -purge");
-      }
+		if (check_label("map_cells")) {
+			if (!noiopads)
+				run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
+			if (family_opt == "max10")
+				run("techmap -map +/intel/max10/cells_map.v");
+			else if (family_opt == "a10gx")
+				run("techmap -map +/intel/a10gx/cells_map.v");
+			else if (family_opt == "cyclonev")
+				run("techmap -map +/intel/cyclonev/cells_map.v");
+			else if (family_opt == "cyclone10")
+				run("techmap -map +/intel/cyclone10/cells_map.v");
+			else if (family_opt == "cycloneiv")
+				run("techmap -map +/intel/cycloneiv/cells_map.v");
+			else
+				run("techmap -map +/intel/cycloneive/cells_map.v");
+			run("dffinit -highlow -ff dffeas q power_up");
+			run("clean -purge");
+		}
 
-    if (check_label("check"))
-      {
-        run("hierarchy -check");
-        run("stat");
-        run("check -noinit");
-      }
+		if (check_label("check")) {
+			run("hierarchy -check");
+			run("stat");
+			run("check -noinit");
+		}
 
-    if (check_label("vqm"))
-      {
-        if (!vout_file.empty() || help_mode)
-          run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s",
-                      help_mode ? "<file-name>" : vout_file.c_str()));
-      }
+		if (check_label("vqm")) {
+			if (!vout_file.empty() || help_mode)
+				run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s",
+					    help_mode ? "<file-name>" : vout_file.c_str()));
+		}
 
-    if (check_label("vpr"))
-      {
-        if (!blif_file.empty() || help_mode)
-          {
-            run(stringf("opt_clean -purge"));
-            run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()));
-          }
-      }
-  }
+		if (check_label("vpr")) {
+			if (!blif_file.empty() || help_mode) {
+				run(stringf("opt_clean -purge"));
+				run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()));
+			}
+		}
+	}
 } SynthIntelPass;
 
 PRIVATE_NAMESPACE_END
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 729cda139..f566a8584 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -18,12 +18,14 @@
  */
 
 // Convert negative-polarity reset to positive-polarity
-module  \$_DFF_NN0_ (input D, C, R, output Q); \$_DFF_NP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-module  \$_DFF_PN0_ (input D, C, R, output Q); \$_DFF_PP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-
-module  \$_DFF_NN1_ (input D, C, R, output Q); \$_DFF_NP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-module  \$_DFF_PN1_ (input D, C, R, output Q); \$_DFF_PP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-
+(* techmap_celltype = "$_DFF_NN0_" *)
+module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_DFF_PN0_" *)
+module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_DFF_NN1_" *)
+module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_DFF_PN1_" *)
+module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1   _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
 
 module \$__SHREG_ (input C, input D, input E, output Q);
   parameter DEPTH = 0;
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a1c4acf7e..e9a3b53a0 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -42,6 +42,10 @@ struct SynthXilinxPass : public ScriptPass
 		log("    -top <module>\n");
 		log("        use the specified module as top module\n");
 		log("\n");
+		log("    -arch {xcup|xcu|xc7|xc6s}\n");
+		log("        run synthesis for the specified Xilinx architecture\n");
+		log("        default: xc7\n");
+		log("\n");
 		log("    -edif <file>\n");
 		log("        write the design to the specified edif file. writing of an output file\n");
 		log("        is omitted if this parameter is not specified.\n");
@@ -89,7 +93,7 @@ struct SynthXilinxPass : public ScriptPass
 		log("\n");
 	}
 
-	std::string top_opt, edif_file, blif_file, abc;
+	std::string top_opt, edif_file, blif_file, abc, arch;
 	bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl, nomux;
 
 	void clear_flags() YS_OVERRIDE
@@ -101,10 +105,12 @@ struct SynthXilinxPass : public ScriptPass
 		flatten = false;
 		retime = false;
 		vpr = false;
+		nocarry = false;
 		nobram = false;
 		nodram = false;
 		nosrl = false;
 		nomux = false;
+		arch = "xc7";
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -119,6 +125,10 @@ struct SynthXilinxPass : public ScriptPass
 				top_opt = "-top " + args[++argidx];
 				continue;
 			}
+			if (args[argidx] == "-arch" && argidx+1 < args.size()) {
+				arch = args[++argidx];
+				continue;
+			}
 			if (args[argidx] == "-edif" && argidx+1 < args.size()) {
 				edif_file = args[++argidx];
 				continue;
@@ -175,6 +185,9 @@ struct SynthXilinxPass : public ScriptPass
 		}
 		extra_args(args, argidx, design);
 
+		if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s")
+			log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str());
+
 		if (!design->full_selection())
 			log_cmd_error("This command only operates on fully selected designs!\n");
 
@@ -291,7 +304,7 @@ struct SynthXilinxPass : public ScriptPass
 
 		if (check_label("check")) {
 			run("hierarchy -check");
-			run("stat");
+			run("stat -tech xilinx");
 			run("check -noinit");
 		}