Carry in/out to be the last input/output for chains to be preserved

2 files changed, 15 insertions, 12 deletions

diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box
index b3972ddb3..6e9e1faf6 100644
--- a/techlibs/xilinx/abc.box
+++ b/techlibs/xilinx/abc.box
@@ -12,17 +12,20 @@ MUXF8 2 1 3 1
 104 94 273
 
 # CARRY4 + CARRY4_[ABCD]X
-# Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3
-# Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3
+# Inputs: S0 S1 S2 S3 CYINIT DI0 DI1 DI2 DI3 CI
+# Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
+#   (NB: carry chain input/output must be last input/output,
+#        swapped with what normally would have been the last
+#        output, here: CI <-> S, CO <-> O
 CARRY4 3 1 10 8
-271 536 379 -   -   -   340 -   -   -
-157 494 465 445 -   -   433 469 -   -
-228 592 540 520 356 -   512 548 292 -
-114 580 526 507 398 385 508 528 378 380
-222 482 -   -   -   -   223 -   -   -
-334 598 407 -   -   -   400 205 -   -
-239 584 556 537 -   -   523 558 226 -
-313 642 615 596 438 -   582 618 330 227
+223 -   -   -   482 -   -   -   -   222
+400 205 -   -   598 407 -   -   -   334
+523 558 226 -   584 556 537 -   -   239
+582 618 330 227 642 615 596 438 -   313
+340 -   -   -   536 379 -   -   -   271
+433 469 -   -   494 465 445 -   -   157
+512 548 292 -   592 540 520 356 -   228
+508 528 378 380 580 526 507 398 385 114
 
 # SLICEM/A6LUT
 # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 29c79f689..120370860 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -173,8 +173,8 @@ module XORCY(output O, input CI, LI);
   assign O = CI ^ LI;
 endmodule
 
-(* abc_box_id = 3, lib_whitebox *)
-module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
+(* abc_box_id = 3, lib_whitebox, abc_carry *)
+module CARRY4((* abc_carry_out *) output [3:0] CO, output [3:0] O, (* abc_carry_in *) input CI, input CYINIT, input [3:0] DI, S);
   assign O = S ^ {CO[2:0], CI | CYINIT};
   assign CO[0] = S[0] ? CI | CYINIT : DI[0];
   assign CO[1] = S[1] ? CO[0] : DI[1];