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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-30 13:07:29 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-30 13:07:29 -0700 |
| commit | 1ad33c3b5ac91fc4e6cb6e2ff4b606a693838c2b (patch) | |
| tree | 84c17326c0fed8c5cb58c97fabbd42e7da93b5d5 /techlibs | |
| parent | e3c8132d7acaae328adeb8d4db1857275b5e8323 (diff) | |
| download | yosys-1ad33c3b5ac91fc4e6cb6e2ff4b606a693838c2b.tar.gz yosys-1ad33c3b5ac91fc4e6cb6e2ff4b606a693838c2b.tar.bz2 yosys-1ad33c3b5ac91fc4e6cb6e2ff4b606a693838c2b.zip | |
Remove whitebox attribute from DRAMs for now
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 120370860..7337e0ea7 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -281,7 +281,7 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule -(* abc_box_id = 4, lib_whitebox *) +(* abc_box_id = 4 /*, lib_whitebox*/ *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@ -301,7 +301,7 @@ module RAM64X1D ( `endif endmodule -(* abc_box_id = 5, lib_whitebox *) +(* abc_box_id = 5 /*, lib_whitebox*/ *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE, |