| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | mux_map to drop sign bit, and eliminate 'bx-es | Eddie Hung | 2019-06-20 | 1 | -13/+47 |
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| * | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-06-20 | 1 | -1/+1 |
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| | * | Fixed small typo in ice40_unlut help summary | acw1251 | 2019-06-19 | 1 | -1/+1 |
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| | * | Fixed the help summary line for a few commands | acw1251 | 2019-06-19 | 1 | -1/+1 |
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| * | | Merge remote-tracking branch 'origin/xaig' into xc7mux | Eddie Hung | 2019-06-18 | 1 | -29/+27 |
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| | * | | Really permute Xilinx LUT mappings as default LUT6.I5:A6 | Eddie Hung | 2019-06-18 | 1 | -16/+16 |
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| | * | | Revert "Fix (do not) permute LUT inputs, but permute mux selects" | Eddie Hung | 2019-06-18 | 1 | -33/+31 |
| | | | | | | | | | | | | | This reverts commit da3d2eedd2b6391621e81b3eaaa28a571e058f9d. | ||||
| * | | | Merge remote-tracking branch 'origin/xaig' into xc7mux | Eddie Hung | 2019-06-18 | 2 | -37/+37 |
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| | * | | Clean up | Eddie Hung | 2019-06-18 | 1 | -6/+4 |
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| | * | | Fix (do not) permute LUT inputs, but permute mux selects | Eddie Hung | 2019-06-18 | 1 | -31/+33 |
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| * | | | Merge remote-tracking branch 'origin/xaig' into xc7mux | Eddie Hung | 2019-06-17 | 1 | -9/+8 |
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| | * | | Fix copy-pasta issue | Eddie Hung | 2019-06-17 | 1 | -9/+8 |
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| * | | | Merge remote-tracking branch 'origin/xaig' into xc7mux | Eddie Hung | 2019-06-17 | 2 | -33/+59 |
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| | * | | Permute INIT for +/xilinx/lut_map.v | Eddie Hung | 2019-06-17 | 1 | -32/+58 |
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| | * | | Simplify comment | Eddie Hung | 2019-06-17 | 1 | -1/+1 |
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| * | | | Merge remote-tracking branch 'origin/xaig' into xc7mux | Eddie Hung | 2019-06-17 | 1 | -5/+5 |
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| | * | | Update LUT7/8 delays to take account for [ABC]OUTMUX delay | Eddie Hung | 2019-06-17 | 1 | -5/+5 |
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| | * | | Try -W 300 | Eddie Hung | 2019-06-17 | 1 | -1/+2 |
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| * | | | Try -W 300 | Eddie Hung | 2019-06-16 | 1 | -1/+2 |
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| * | | | Merge remote-tracking branch 'origin/xaig' into xc7mux | Eddie Hung | 2019-06-15 | 1 | -2/+2 |
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| | * | | Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O | Eddie Hung | 2019-06-15 | 1 | -2/+2 |
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| * | | | Revert "Remove wide mux inference" | Eddie Hung | 2019-06-14 | 4 | -3/+194 |
| |/ / | | | | | | | This reverts commit 738fdfe8f55e18ac7f315cd68c117eae370004ca. | ||||
| * | | As per @daveshah1 remove async DFF timing from xilinx | Eddie Hung | 2019-06-14 | 1 | -2/+2 |
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| * | | Resolve comments from @daveshah1 | Eddie Hung | 2019-06-14 | 1 | -1/+1 |
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| * | | Add XC7_WIRE_DELAY macro to synth_xilinx.cc | Eddie Hung | 2019-06-14 | 1 | -1/+3 |
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| * | | Update delays based on SymbiFlow/prjxray-db | Eddie Hung | 2019-06-14 | 1 | -12/+13 |
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| * | | Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut} | Eddie Hung | 2019-06-14 | 4 | -3/+3 |
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| * | | Comment out dist RAM boxing on ECP5 for now | Eddie Hung | 2019-06-14 | 1 | -1/+1 |
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| * | | Remove WIP ABC9 flop support | Eddie Hung | 2019-06-14 | 4 | -46/+46 |
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| * | | Make doc consistent | Eddie Hung | 2019-06-14 | 3 | -3/+6 |
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| * | | ecp5: Add abc9 option | David Shah | 2019-06-14 | 6 | -70/+184 |
| | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | Fix name clash | Eddie Hung | 2019-06-13 | 1 | -4/+8 |
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| * | | Fix LP SB_LUT4 timing | Eddie Hung | 2019-06-13 | 1 | -1/+1 |
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| * | | Move neg-pol to pos-pol mapping from ff_map to cells_map.v | Eddie Hung | 2019-06-12 | 1 | -0/+8 |
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| * | | Reduce diff with master | Eddie Hung | 2019-06-12 | 1 | -1/+1 |
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| * | | Remove abc_flop{,_d} attributes from ice40/cells_sim.v | Eddie Hung | 2019-06-12 | 1 | -40/+20 |
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| * | | Fix spacing | Eddie Hung | 2019-06-12 | 1 | -6/+6 |
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| * | | Remove wide mux inference | Eddie Hung | 2019-06-12 | 4 | -194/+3 |
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| * | | Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx" | Eddie Hung | 2019-06-12 | 1 | -1/+1 |
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| * | | Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx" | Eddie Hung | 2019-06-12 | 1 | -1/+1 |
| | | | | | | | | | This reverts commit 2dffa4685b830313204f5d04314a14ed6ecac8ec. | ||||
| * | | Add "-W' wire delay arg to abc9, use from synth_xilinx | Eddie Hung | 2019-06-11 | 1 | -1/+1 |
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| * | | Disable dist RAM boxes due to comb loop | Eddie Hung | 2019-06-11 | 1 | -2/+2 |
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| * | | Remove #ifndef ABC | Eddie Hung | 2019-06-11 | 1 | -4/+0 |
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| * | | Revert "Revert "Move ff_map back after ABC for shregmap"" | Eddie Hung | 2019-06-10 | 1 | -5/+5 |
| | | | | | | | | | This reverts commit e473e7456545d702c011ee7872956f94a8522865. | ||||
| * | | Revert "Rename shregmap -tech xilinx -> xilinx_dynamic" | Eddie Hung | 2019-06-10 | 1 | -2/+2 |
| | | | | | | | | | This reverts commit 94a5f4e60985fc1e3fea75eec85638fa29874bea. | ||||
| * | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-06-10 | 1 | -0/+24 |
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| | * | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k | Simon Schubert | 2019-06-10 | 1 | -0/+24 |
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| * | | Comment out muxpack (currently broken) | Eddie Hung | 2019-06-07 | 1 | -2/+2 |
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| * | | $__XILINX_MUX_ -> $__XILINX_SHIFTX | Eddie Hung | 2019-06-06 | 2 | -11/+11 |
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| * | | Fix muxcover and its techmapping | Eddie Hung | 2019-06-06 | 2 | -3/+3 |
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index : iCE40/yosys | |
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