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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 11:38:22 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 11:38:22 -0700 |
| commit | 2e34859a6b9780d6dc2df28dabcab893b5f4ce4a (patch) | |
| tree | 63eff8a19f59dc29fdc1a95af0e8fbde086cb38b /techlibs | |
| parent | ba4b4a0088ff7ae37b86f0c22cf2a95f0aba9e13 (diff) | |
| download | yosys-2e34859a6b9780d6dc2df28dabcab893b5f4ce4a.tar.gz yosys-2e34859a6b9780d6dc2df28dabcab893b5f4ce4a.tar.bz2 yosys-2e34859a6b9780d6dc2df28dabcab893b5f4ce4a.zip | |
Add XC7_WIRE_DELAY macro to synth_xilinx.cc
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 2308ddadd..a11648873 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -25,6 +25,8 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN +#define XC7_WIRE_DELAY "160" + struct SynthXilinxPass : public ScriptPass { SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { } @@ -279,7 +281,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_luts")) { if (abc == "abc9") - run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W 160" + string(retime ? " -dff" : "")); + run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -dff" : "")); else if (help_mode) run(abc + " -luts 2:2,3,6:5,10,20 [-dff]"); else |