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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 12:43:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 12:43:20 -0700 |
| commit | 8fa74287a71fc3527cf48c7fb2c4a635ee832b72 (patch) | |
| tree | ac78e40defe12c75bcc040f973217ad6875bf5af /techlibs | |
| parent | 7876b5b8bef1ff8460e48232e68bb5136f04e7b5 (diff) | |
| download | yosys-8fa74287a71fc3527cf48c7fb2c4a635ee832b72.tar.gz yosys-8fa74287a71fc3527cf48c7fb2c4a635ee832b72.tar.bz2 yosys-8fa74287a71fc3527cf48c7fb2c4a635ee832b72.zip | |
As per @daveshah1 remove async DFF timing from xilinx
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/abc_xc7.box | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index a4182ed63..8a48bad4e 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -54,9 +54,9 @@ FDSE 7 0 4 1 # Inputs: C CE CLR D # Outputs: Q FDCE 8 0 4 1 -- - 404 - +- - - - # Inputs: C CE D PRE # Outputs: Q FDPE 9 0 4 1 -- - - 404 +- - - - |