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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-10 14:34:43 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-10 14:34:43 -0700 |
commit | a1d4ae78a0ee474af6782bc5e12d8bd1fc790f04 (patch) | |
tree | 0a2678fcccc897d651904c42ac1f5dfd34d6dedd /techlibs | |
parent | 7d27e1e4312499b72d253470c97cfbf98e4c9d8e (diff) | |
download | yosys-a1d4ae78a0ee474af6782bc5e12d8bd1fc790f04.tar.gz yosys-a1d4ae78a0ee474af6782bc5e12d8bd1fc790f04.tar.bz2 yosys-a1d4ae78a0ee474af6782bc5e12d8bd1fc790f04.zip |
Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"
This reverts commit 94a5f4e60985fc1e3fea75eec85638fa29874bea.
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ffdb22960..689a40135 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -266,8 +266,8 @@ struct SynthXilinxPass : public ScriptPass // shregmap operates on bit-level flops, not word-level, // so break those down here run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')"); - // shregmap to infer variable length shift regs - run("shregmap -tech xilinx_dynamic -minlen 3", "(skip if '-nosrl')"); + // shregmap with '-tech xilinx' infers variable length shift regs + run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')"); } std::string techmap_files = " -map +/techmap.v"; |