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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-11 17:10:47 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-11 17:10:47 -0700 |
| commit | 2dffa4685b830313204f5d04314a14ed6ecac8ec (patch) | |
| tree | 023b8e9760f344f59f26efbe3912c3f610ff8bfe /techlibs | |
| parent | d26646051c4ae9740decd5d76eec6a3afd63844a (diff) | |
| download | yosys-2dffa4685b830313204f5d04314a14ed6ecac8ec.tar.gz yosys-2dffa4685b830313204f5d04314a14ed6ecac8ec.tar.bz2 yosys-2dffa4685b830313204f5d04314a14ed6ecac8ec.zip | |
Add "-W' wire delay arg to abc9, use from synth_xilinx
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index f5f8c43e0..f966115cd 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -297,7 +297,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_luts")) { if (abc == "abc9") - run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : "")); + run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box -W 160" + string(retime ? " -dff" : "")); else if (help_mode) run(abc + " -luts 2:2,3,6:5,10,20 [-dff]"); else |