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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-16 12:08:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-17 10:29:06 -0700 |
| commit | c15ee827f4a171abe3108dba8f9ad0d7078eb306 (patch) | |
| tree | 483151ccc000cc13ad95d074e1c90aceabe90d75 /techlibs | |
| parent | 7250c57c5a05139ca03544a31fe40b52e4e73486 (diff) | |
| download | yosys-c15ee827f4a171abe3108dba8f9ad0d7078eb306.tar.gz yosys-c15ee827f4a171abe3108dba8f9ad0d7078eb306.tar.bz2 yosys-c15ee827f4a171abe3108dba8f9ad0d7078eb306.zip | |
Try -W 300
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index a11648873..45bc47f24 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -25,7 +25,8 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -#define XC7_WIRE_DELAY "160" +#define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate + // to one LUT6 (instead of a LUT5 + LUT2) struct SynthXilinxPass : public ScriptPass { |