Revert "Fix (do not) permute LUT inputs, but permute mux selects"

This reverts commit da3d2eedd2b6391621e81b3eaaa28a571e058f9d.

1 files changed, 31 insertions, 33 deletions

diff --git a/techlibs/xilinx/lut_map.v b/techlibs/xilinx/lut_map.v
index 62ce374df..2f246e46d 100644
--- a/techlibs/xilinx/lut_map.v
+++ b/techlibs/xilinx/lut_map.v
@@ -29,32 +29,30 @@ module \$lut (A, Y);
   input [WIDTH-1:0] A;
   output Y;
 
-  // Need to swap input ordering of wide LUTs, and fix init accordingly,
+  // Need to swap input ordering, and fix init accordingly,
   // to match ABC's expectation of LUT inputs in non-decreasing
   // delay order
   function [WIDTH-1:0] permute_index;
       input [WIDTH-1:0] i;
       integer j;
       begin
-          if (WIDTH == 7)
-              permute_index = { i[5:0], i[6] };
-          else if (WIDTH == 8)
-              permute_index = { i[5:0], i[6], i[7] };
-          else
-              permute_index = i;
+          permute_index = 0;
+          for (j = 0; j < WIDTH; j = j + 1)
+              permute_index[WIDTH-1 - j] = i[j];
       end
   endfunction
 
   function [2**WIDTH-1:0] permute_init;
+      input [2**WIDTH-1:0] orig;
       integer i;
       begin
           permute_init = 0;
           for (i = 0; i < 2**WIDTH; i = i + 1)
-              permute_init[i] = LUT[permute_index(i)];
+              permute_init[i] = orig[permute_index(i)];
       end
   endfunction
 
-  parameter [2**WIDTH-1:0] P_LUT = permute_init();
+  parameter [2**WIDTH-1:0] P_LUT = permute_init(LUT);
 
   generate
     if (WIDTH == 1) begin
@@ -63,54 +61,54 @@ module \$lut (A, Y);
     end else
     if (WIDTH == 2) begin
       LUT2 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]));
+        .I0(A[1]), .I1(A[0]));
     end else
     if (WIDTH == 3) begin
       LUT3 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]));
+        .I0(A[2]), .I1(A[1]), .I2(A[0]));
     end else
     if (WIDTH == 4) begin
       LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]),
-        .I3(A[3]));
+        .I0(A[3]), .I1(A[2]), .I2(A[1]),
+        .I3(A[0]));
     end else
     if (WIDTH == 5) begin
       LUT5 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]),
-        .I3(A[3]), .I4(A[4]));
+        .I0(A[4]), .I1(A[3]), .I2(A[2]),
+        .I3(A[1]), .I4(A[0]));
     end else
     if (WIDTH == 6) begin
       LUT6 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]),
-        .I3(A[3]), .I4(A[4]), .I5(A[5]));
+        .I0(A[5]), .I1(A[4]), .I2(A[3]),
+        .I3(A[2]), .I4(A[1]), .I5(A[0]));
     end else
     if (WIDTH == 7) begin
       wire T0, T1;
       LUT6 #(.INIT(P_LUT[63:0])) fpga_lut_0 (.O(T0),
-        .I0(A[1]), .I1(A[2]), .I2(A[3]),
-        .I3(A[4]), .I4(A[5]), .I5(A[6]));
+        .I0(A[5]), .I1(A[4]), .I2(A[3]),
+        .I3(A[2]), .I4(A[1]), .I5(A[0]));
       LUT6 #(.INIT(P_LUT[127:64])) fpga_lut_1 (.O(T1),
-        .I0(A[1]), .I1(A[2]), .I2(A[3]),
-        .I3(A[4]), .I4(A[5]), .I5(A[6]));
-      MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[0]));
+        .I0(A[5]), .I1(A[4]), .I2(A[3]),
+        .I3(A[2]), .I4(A[1]), .I5(A[0]));
+      MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[6]));
     end else
     if (WIDTH == 8) begin
       wire T0, T1, T2, T3, T4, T5;
       LUT6 #(.INIT(P_LUT[63:0])) fpga_lut_0 (.O(T0),
-        .I0(A[2]), .I1(A[3]), .I2(A[4]),
-        .I3(A[5]), .I4(A[6]), .I5(A[7]));
+        .I0(A[5]), .I1(A[4]), .I2(A[3]),
+        .I3(A[2]), .I4(A[1]), .I5(A[0]));
       LUT6 #(.INIT(P_LUT[127:64])) fpga_lut_1 (.O(T1),
-        .I0(A[2]), .I1(A[3]), .I2(A[4]),
-        .I3(A[5]), .I4(A[6]), .I5(A[7]));
+        .I0(A[5]), .I1(A[4]), .I2(A[3]),
+        .I3(A[2]), .I4(A[1]), .I5(A[0]));
       LUT6 #(.INIT(P_LUT[191:128])) fpga_lut_2 (.O(T2),
-        .I0(A[2]), .I1(A[3]), .I2(A[4]),
-        .I3(A[5]), .I4(A[6]), .I5(A[7]));
+        .I0(A[5]), .I1(A[4]), .I2(A[3]),
+        .I3(A[2]), .I4(A[1]), .I5(A[0]));
       LUT6 #(.INIT(P_LUT[255:192])) fpga_lut_3 (.O(T3),
-        .I0(A[2]), .I1(A[3]), .I2(A[4]),
-        .I3(A[5]), .I4(A[6]), .I5(A[7]));
-      MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[1]));
-      MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[1]));
-      MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[0]));
+        .I0(A[5]), .I1(A[4]), .I2(A[3]),
+        .I3(A[2]), .I4(A[1]), .I5(A[0]));
+      MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[6]));
+      MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[6]));
+      MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[7]));
     end else begin
       wire _TECHMAP_FAIL_ = 1;
     end