add silence detection

6 files changed, 96 insertions, 104 deletions

diff --git a/Makefile b/Makefile
index 2373f0c..b4eb14e 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 PROJ=spdif
 
 SRCS=$(wildcard *.vhd *.v *.qsf *.qpf )
-TIDY_SRC= bmc_decoder.vhd ccd.vhd clock_recovery.vhd counter.vhd dflipflop.vhd spdif_decoder.vhd spdif.vhd
+TIDY_SRC= bmc_decoder.vhd ccd.vhd silence_detector.vhd counter.vhd dflipflop.vhd spdif_decoder.vhd spdif.vhd
 
 SOF=${PROJ}.sof
 POF=${PROJ}.pof
diff --git a/clock_recovery.vhd b/clock_recovery.vhd
deleted file mode 100644
index 91de224..0000000
--- a/clock_recovery.vhd
+++ /dev/null
@@ -1,82 +0,0 @@
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.std_logic_unsigned.all;
-use IEEE.numeric_std.all;
-
-entity clock_recovery is
-    port
-        (
-            n_reset : in std_logic;
-
-            clk     : in  std_logic;
-            d_in    : in  std_logic;
-            clk_out : out std_logic
-            );
-end clock_recovery;
-
-architecture rtl of clock_recovery is
-
-
-    signal qish :
-        std_logic;
-    signal od :
-        std_logic;
-    signal edge :
-        std_logic;
-    signal period :
-        std_logic_vector(15 downto 0);
-    signal divisor :
-        std_logic_vector(15 downto 0);
-    signal counter :
-        std_logic_vector(15 downto 0);
-begin
-
-
-    process(clk, d_in, od, n_reset)
-    begin
-        if n_reset = '0' then
-            od <= '0';
-        elsif RISING_EDGE(clk) then
-            od <= d_in;
-        end if;
-    end process;
-
-    edge    <= d_in xor od;
-    divisor <= x"0007";
-
-    process(edge, n_reset, clk, divisor, counter, qish, period)
-    begin
-        if n_reset = '0' then
-            period  <= (others => '0');
-            counter <= (others => '0');
-            qish    <= '0';
-        elsif RISING_EDGE(clk) then
-            if edge = '0' then
-                period <= period +1;
-
-                if counter < divisor then
-                    counter <= counter + 1;
-                else
-                    counter <= (others => '0');
-                    qish    <= not qish;
-                end if;
-            else
-                period  <= (others => '0');
-                counter <= (others => '0');
-                qish    <= '0';
--- if period<divisor then
--- divisor <= divisor -1;
--- else
--- divisor <= divisor + 1;
--- end if;
-
-            end if;
-        end if;
-    end process;
-
-    clk_out <= qish;
-
-end rtl;
-
diff --git a/counter.vhd b/counter.vhd
index 4ae6a2a..0be542f 100644
--- a/counter.vhd
+++ b/counter.vhd
@@ -8,7 +8,7 @@ use IEEE.numeric_std.all;
 entity counter is
     port
         (
-            divisor : in  std_logic_vector(15 downto 0) := (others => '0');
+            divisor : in  integer;
             clk     : in  std_logic;
             n_reset : in  std_logic;
             clk_out : out std_logic
diff --git a/silence_detector.vhd b/silence_detector.vhd
new file mode 100644
index 0000000..fe85824
--- /dev/null
+++ b/silence_detector.vhd
@@ -0,0 +1,54 @@
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.numeric_std.all;
+
+entity silence_detector is
+    port
+        (
+            max_ticks : in  integer;
+            clk       : in  std_logic;
+            d         : in  std_logic_vector(23 downto 0);
+            n_reset   : in  std_logic;
+            silent    : out std_logic
+            );
+end silence_detector;
+
+
+architecture rtl of silence_detector is
+
+    signal ticks      : std_logic_vector (31 downto 0);
+    signal last_d     : std_logic_vector (23 downto 0);
+    signal silent_buf : std_logic;
+
+begin
+
+    process (last_d, d, clk, max_ticks, ticks)
+    begin
+        if n_reset = '0' then
+            ticks      <= (others => '0');
+            silent_buf <= '0';
+            last_d     <= (others => '0');
+        elsif rising_edge(clk) then
+            last_d <= d;
+
+            if last_d = d then
+                if ticks < max_ticks then
+                    ticks <= ticks +1;
+                else
+                    silent_buf <= '1';
+                end if;
+            else
+                ticks      <= (others => '0');
+                silent_buf <= '0';
+            end if;
+        end if;
+    end process;
+
+
+    silent <= silent_buf;
+
+end rtl;
+
diff --git a/spdif.qsf b/spdif.qsf
index b57bdf8..e1ddff1 100644
--- a/spdif.qsf
+++ b/spdif.qsf
@@ -31,7 +31,6 @@ set_location_assignment PIN_114 -to n_stby_out
 set_location_assignment PIN_41 -to dbg1
 set_location_assignment PIN_101 -to dbg2
 set_global_assignment -name VHDL_FILE ccd.vhd
-set_global_assignment -name VHDL_FILE clock_recovery.vhd
 set_global_assignment -name VHDL_FILE counter.vhd
 set_global_assignment -name VHDL_FILE dflipflop.vhd
 set_global_assignment -name VHDL_FILE pll100.vhd
@@ -39,6 +38,7 @@ set_global_assignment -name VHDL_FILE pll200.vhd
 set_global_assignment -name VHDL_FILE spdif.vhd
 set_global_assignment -name VHDL_FILE bmc_decoder.vhd
 set_global_assignment -name VHDL_FILE spdif_decoder.vhd
+set_global_assignment -name VHDL_FILE silence_detector.vhd
 set_global_assignment -name SOURCE_FILE db/spdif.cmp.rdb
 set_global_assignment -name SDC_FILE spdif.sdc
 
diff --git a/spdif.vhd b/spdif.vhd
index cb55844..5ee9a3c 100644
--- a/spdif.vhd
+++ b/spdif.vhd
@@ -52,17 +52,17 @@ architecture rtl of spdif is
             locked : out std_logic
             );
     end component;
+
     component counter is
         port
             (
-                divisor : in  std_logic_vector (15 downto 0);
+                divisor : in  integer;
                 clk     : in  std_logic;
                 n_reset : in  std_logic;
                 clk_out : out std_logic
                 );
     end component;
 
-
     component spdif_decoder is
         port
             (
@@ -80,6 +80,20 @@ architecture rtl of spdif is
                 );
     end component;
 
+
+    component silence_detector is
+        port
+            (
+                max_ticks : in  integer;
+                clk       : in  std_logic;
+                d         : in  std_logic_vector(23 downto 0);
+                n_reset   : in  std_logic;
+                silent    : out std_logic
+                );
+    end component;
+
+
+
     signal n_reset :
         std_logic;
     signal clk_200mhz :
@@ -90,9 +104,12 @@ architecture rtl of spdif is
         std_logic;
     signal clk1 :
         std_logic;
-    signal d1   : std_logic_vector(26 downto 0);
-    signal bna1 : std_logic;
-    signal sof1 : std_logic;
+    signal d1     : std_logic_vector(26 downto 0);
+    signal bna1   : std_logic;
+    signal sof1   : std_logic;
+    signal ready1 : std_logic;
+
+    signal mute1 : std_logic;
 
 begin
     n_reset <= n_rst_in;
@@ -105,17 +122,10 @@ begin
             c0     => clk_200mhz
             );
 
---    pll2 :
---        pll200 port map (
---            areset => not n_reset,
---            inclk0 => xtal_50mhz,
---            c0     => clk_100mhz
---            );
-
     div1 : counter port map (
         n_reset => n_reset,
         clk     => clk_200mhz,
-        divisor => x"000c",
+        divisor => 6,
         clk_out => clk1
         );
 
@@ -137,21 +147,31 @@ begin
         bmc_d     => dbg6,
         bna       => bna1,
         d         => d1,
-        ready     => dbg7
+        ready     => ready1
         );
 
+
     dbg8 <= bna1;
 
+    sd1 : silence_detector port map(
+        n_reset   => n_reset,
+        clk       => clk1,
+        d         => d1(26 downto 3),
+        max_ticks => 33333333,          -- 1 second
+        silent    => mute1
+        );
+
+    n_mute_out <= not mute1;
+    n_stby_out <= '0';
 
     dbg1 <= spdif_clkd1;
     dbg2 <= clk1;
+    dbg7 <= ready1;
 
+    n_leds(0) <= d1(26);
+    n_leds(1) <= d1(25);
+    n_leds(2) <= not mute1;
 
-    n_leds(0) <= d1(9);
-    n_leds(1) <= d1(10);
-    n_leds(2) <= d1(11);
 
-    n_mute_out <= '0';
-    n_stby_out <= '0';
 
 end rtl;