1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity spdif is
port (
xtal_50mhz : in std_logic;
spdif_in : in std_logic;
n_rst_in : in std_logic;
n_leds : out std_logic_vector(2 downto 0);
n_mute_out : out std_logic;
n_stby_out : out std_logic;
dbg1 : out std_logic;
dbg2 : out std_logic;
dbg3 : out std_logic;
dbg4 : out std_logic;
dbg5 : out std_logic;
dbg6 : out std_logic;
dbg7 : out std_logic;
dbg8 : out std_logic
);
end spdif;
architecture rtl of spdif is
component ccd is
port
(
n_reset : in std_logic;
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end component;
component pll100 is
port (
areset : in std_logic := '0';
inclk0 : in std_logic := '0';
c0 : out std_logic;
locked : out std_logic
);
end component;
component pll200 is
port (
areset : in std_logic := '0';
inclk0 : in std_logic := '0';
c0 : out std_logic;
locked : out std_logic
);
end component;
component counter is
port
(
divisor : in integer;
clk : in std_logic;
n_reset : in std_logic;
clk_out : out std_logic
);
end component;
component spdif_decoder is
port
(
n_reset : in std_logic;
clk : in std_logic;
spdif : in std_logic;
bmc_ready : out std_logic;
bmc_e : out std_logic;
bmc_l : out std_logic;
bmc_d : out std_logic;
sof : out std_logic;
bna : out std_logic;
d : out std_logic_vector(26 downto 0);
ready : out std_logic
);
end component;
component silence_detector is
port
(
max_ticks : in integer;
clk : in std_logic;
d : in std_logic_vector(23 downto 0);
n_reset : in std_logic;
silent : out std_logic
);
end component;
signal n_reset :
std_logic;
signal clk_200mhz :
std_logic;
-- signal clk_100mhz :
-- std_logic;
signal spdif_clkd1 :
std_logic;
signal clk1 :
std_logic;
signal d1 : std_logic_vector(26 downto 0);
signal bna1 : std_logic;
signal sof1 : std_logic;
signal ready1 : std_logic;
signal mute1 : std_logic;
begin
n_reset <= n_rst_in;
pll1 :
pll200 port map (
areset => not n_reset,
inclk0 => xtal_50mhz,
c0 => clk_200mhz
);
div1 : counter port map (
n_reset => n_reset,
clk => clk_200mhz,
divisor => 6,
clk_out => clk1
);
b1 :
ccd port map (
n_reset => n_reset,
clk => clk1,
d => spdif_in,
q => spdif_clkd1
);
dec1 : spdif_decoder port map (
n_reset => n_reset,
clk => clk1,
spdif => spdif_clkd1,
bmc_ready => dbg3,
bmc_e => dbg4,
bmc_l => dbg5,
bmc_d => dbg6,
bna => bna1,
d => d1,
ready => ready1
);
dbg8 <= bna1;
sd1 : silence_detector port map(
n_reset => n_reset,
clk => clk1,
d => d1(26 downto 3),
max_ticks => 33333333, -- 1 second
silent => mute1
);
n_mute_out <= not mute1;
n_stby_out <= '0';
dbg1 <= spdif_clkd1;
dbg2 <= clk1;
dbg7 <= ready1;
n_leds(0) <= d1(26);
n_leds(1) <= d1(25);
n_leds(2) <= not mute1;
end rtl;
|
