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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity silence_detector is
port
(
max_ticks : in integer;
clk : in std_logic;
d : in std_logic_vector(23 downto 0);
n_reset : in std_logic;
silent : out std_logic
);
end silence_detector;
architecture rtl of silence_detector is
signal ticks : std_logic_vector (31 downto 0);
signal last_d : std_logic_vector (23 downto 0);
signal silent_buf : std_logic;
begin
process (last_d, d, clk, max_ticks, ticks)
begin
if n_reset = '0' then
ticks <= (others => '0');
silent_buf <= '0';
last_d <= (others => '0');
elsif rising_edge(clk) then
last_d <= d;
if last_d = d then
if ticks < max_ticks then
ticks <= ticks +1;
else
silent_buf <= '1';
end if;
else
ticks <= (others => '0');
silent_buf <= '0';
end if;
end if;
end process;
silent <= silent_buf;
end rtl;
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