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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity clock_recovery is
port
(
n_reset : in std_logic;
clk : in std_logic;
d_in : in std_logic;
clk_out : out std_logic
);
end clock_recovery;
architecture rtl of clock_recovery is
signal qish :
std_logic;
signal od :
std_logic;
signal edge :
std_logic;
signal period :
std_logic_vector(15 downto 0);
signal divisor :
std_logic_vector(15 downto 0);
signal counter :
std_logic_vector(15 downto 0);
begin
process(clk, d_in, od, n_reset)
begin
if n_reset = '0' then
od <= '0';
elsif RISING_EDGE(clk) then
od <= d_in;
end if;
end process;
edge <= d_in xor od;
divisor <= x"0007";
process(edge, n_reset, clk, divisor, counter, qish, period)
begin
if n_reset = '0' then
period <= (others => '0');
counter <= (others => '0');
qish <= '0';
elsif RISING_EDGE(clk) then
if edge = '0' then
period <= period +1;
if counter < divisor then
counter <= counter + 1;
else
counter <= (others => '0');
qish <= not qish;
end if;
else
period <= (others => '0');
counter <= (others => '0');
qish <= '0';
-- if period<divisor then
-- divisor <= divisor -1;
-- else
-- divisor <= divisor + 1;
-- end if;
end if;
end if;
end process;
clk_out <= qish;
end rtl;
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