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authorJames <31272717+gpd-pocket-hacker@users.noreply.github.com>2018-05-17 17:46:40 +0100
committerJames <31272717+gpd-pocket-hacker@users.noreply.github.com>2018-05-17 17:46:40 +0100
commit3769dd04597e39140755bd4b92023570e6fcde3c (patch)
tree2fe48152e573b383d073917868c559bdd8e20601
parent297375cf51e449ebd4a11aa05b0011016e40f72f (diff)
downloadrob_spdif-3769dd04597e39140755bd4b92023570e6fcde3c.zip
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tidy
-rw-r--r--counter.vhd8
-rw-r--r--detector.vhd108
-rw-r--r--divider.vhd38
-rw-r--r--silence_detector.vhd88
-rw-r--r--spdif.qpf34
-rw-r--r--spdif.qsf102
-rw-r--r--spdif.vhd82
-rw-r--r--spdif_decoder.vhd52
8 files changed, 256 insertions, 256 deletions
diff --git a/counter.vhd b/counter.vhd
index 9fad8b3..e77b1a5 100644
--- a/counter.vhd
+++ b/counter.vhd
@@ -8,9 +8,9 @@ use IEEE.numeric_std.all;
entity counter is
port
(
- divisor : in integer;
- clk : in std_logic;
- n_reset : in std_logic;
+ divisor : in integer;
+ clk : in std_logic;
+ n_reset : in std_logic;
pulse_out : out std_logic
);
end counter;
@@ -34,7 +34,7 @@ begin
if d < divisor then
d <= d + 1;
- q<='0';
+ q <= '0';
else
d <= (others => '0');
q <= '1';
diff --git a/detector.vhd b/detector.vhd
index b6e598f..c97ecd3 100644
--- a/detector.vhd
+++ b/detector.vhd
@@ -5,15 +5,15 @@ use IEEE.numeric_std.all;
entity detector is
port (
- clk_in : in std_logic;
- spdif_in: in std_logic;
- n_reset : in std_logic;
- divisor : in integer;
- silent_thresh : in integer;
- valid_divisor: in integer;
- valid_thresh : in integer;
- mute : out std_logic;
- dbg:out std_logic_vector(7 downto 0)
+ clk_in : in std_logic;
+ spdif_in : in std_logic;
+ n_reset : in std_logic;
+ divisor : in integer;
+ silent_thresh : in integer;
+ valid_divisor : in integer;
+ valid_thresh : in integer;
+ mute : out std_logic;
+ dbg : out std_logic_vector(7 downto 0)
);
end detector;
@@ -40,23 +40,23 @@ architecture rtl of detector is
end component;
component spdif_decoder is
-port (
- n_reset:in std_logic;
- spdif:in std_logic;
- clk:in std_logic;
+ port (
+ n_reset : in std_logic;
+ spdif : in std_logic;
+ clk : in std_logic;
+
+ bmc_ready : out std_logic;
+ bmc_e : out std_logic;
+ bmc_l : out std_logic;
+ bmc_d : out std_logic;
+
+ d : out std_logic_vector(26 downto 0);
+ ready : out std_logic;
+ sof : out std_logic;
+ bna : out std_logic;
+ sos : out std_logic
+ );
- bmc_ready: out std_logic;
- bmc_e: out std_logic;
- bmc_l: out std_logic;
- bmc_d : out std_logic;
-
- d : out std_logic_vector(26 downto 0);
- ready: out std_logic;
- sof: out std_logic;
- bna: out std_logic;
- sos: out std_logic
-);
-
@@ -65,31 +65,31 @@ port (
component silence_detector is
- port
- (
- silent_thresh : in integer;
- valid_thresh : in integer;
- valid_divisor : in integer;
-
- clk : in std_logic;
- sos : in std_logic;
- d : in std_logic_vector(23 downto 0);
- n_reset : in std_logic;
- silent : out std_logic;
- valid : out std_logic;
- dbg:out std_logic
- );
+ port
+ (
+ silent_thresh : in integer;
+ valid_thresh : in integer;
+ valid_divisor : in integer;
+
+ clk : in std_logic;
+ sos : in std_logic;
+ d : in std_logic_vector(23 downto 0);
+ n_reset : in std_logic;
+ silent : out std_logic;
+ valid : out std_logic;
+ dbg : out std_logic
+ );
end component;
signal spdif :
std_logic;
signal clk :
std_logic;
- signal d : std_logic_vector(26 downto 0);
- signal sos : std_logic;
- signal valid : std_logic;
- signal silent:std_logic;
- signal mute_buf:std_logic;
+ signal d : std_logic_vector(26 downto 0);
+ signal sos : std_logic;
+ signal valid : std_logic;
+ signal silent : std_logic;
+ signal mute_buf : std_logic;
begin
div1 : divider port map (
@@ -112,23 +112,23 @@ begin
clk => clk,
spdif => spdif,
d => d,
- sos => sos,
- bmc_ready => dbg(2)
+ sos => sos,
+ bmc_ready => dbg(2)
);
sd : silence_detector port map(
- n_reset => n_reset,
- clk => clk,
- sos => sos,
- d => d(26 downto 3),
+ n_reset => n_reset,
+ clk => clk,
+ sos => sos,
+ d => d(26 downto 3),
silent_thresh => silent_thresh,
valid_thresh => valid_thresh,
- valid_divisor => valid_divisor,
+ valid_divisor => valid_divisor,
- silent => silent,
- valid => valid,
- dbg => dbg(7)
+ silent => silent,
+ valid => valid,
+ dbg => dbg(7)
);
diff --git a/divider.vhd b/divider.vhd
index 26280bf..1a8c2ca 100644
--- a/divider.vhd
+++ b/divider.vhd
@@ -18,37 +18,37 @@ end divider;
architecture rtl of divider is
-component counter is
- port
- (
- divisor : in integer;
- clk : in std_logic;
- n_reset : in std_logic;
- pulse_out : out std_logic
- );
-end component;
-
-
- signal pulse: std_logic;
+ component counter is
+ port
+ (
+ divisor : in integer;
+ clk : in std_logic;
+ n_reset : in std_logic;
+ pulse_out : out std_logic
+ );
+ end component;
+
+
+ signal pulse : std_logic;
signal q :
std_logic;
begin
clk_out <= q;
- c1:counter port map (
- divisor => divisor,
- clk => clk,
- n_reset => n_reset,
- pulse_out => pulse
- );
+ c1 : counter port map (
+ divisor => divisor,
+ clk => clk,
+ n_reset => n_reset,
+ pulse_out => pulse
+ );
process (clk, pulse, n_reset)
begin
if n_reset = '0' then
q <= '0';
- elsif RISING_EDGE(clk) and pulse='1' then
+ elsif RISING_EDGE(clk) and pulse = '1' then
q <= not q;
end if;
end process;
diff --git a/silence_detector.vhd b/silence_detector.vhd
index 5556e68..14cc72e 100644
--- a/silence_detector.vhd
+++ b/silence_detector.vhd
@@ -8,17 +8,17 @@ use IEEE.numeric_std.all;
entity silence_detector is
port
(
- silent_thresh : in integer;
- valid_thresh : in integer;
- valid_divisor : in integer;
-
- clk : in std_logic;
- sos : in std_logic;
- d : in std_logic_vector(23 downto 0);
- n_reset : in std_logic;
- silent : out std_logic;
- valid : out std_logic;
- dbg : out std_logic
+ silent_thresh : in integer;
+ valid_thresh : in integer;
+ valid_divisor : in integer;
+
+ clk : in std_logic;
+ sos : in std_logic;
+ d : in std_logic_vector(23 downto 0);
+ n_reset : in std_logic;
+ silent : out std_logic;
+ valid : out std_logic;
+ dbg : out std_logic
);
end silence_detector;
@@ -28,38 +28,38 @@ architecture rtl of silence_detector is
component counter is
port
(
- divisor : in integer;
- clk : in std_logic;
- n_reset : in std_logic;
+ divisor : in integer;
+ clk : in std_logic;
+ n_reset : in std_logic;
pulse_out : out std_logic
);
end component;
- signal silence : std_logic_vector (31 downto 0);
+ signal silence : std_logic_vector (31 downto 0);
signal last_d : std_logic_vector (23 downto 0);
signal silent_buf : std_logic;
- signal valid_buf : std_logic;
+ signal valid_buf : std_logic;
- signal validity : std_logic_vector(31 downto 0);
+ signal validity : std_logic_vector(31 downto 0);
signal interval : std_logic;
begin
vcnt : counter port map (
- n_reset => n_reset,
- clk => clk,
- divisor => valid_divisor,
- pulse_out =>interval
+ n_reset => n_reset,
+ clk => clk,
+ divisor => valid_divisor,
+ pulse_out => interval
);
process (last_d, d, clk, sos, silent_thresh, silence)
begin
if n_reset = '0' then
- silence <= (others => '0');
- silent_buf <= '0';
- last_d <= (others => '0');
- elsif rising_edge(clk) and sos='1' then
+ silence <= (others => '0');
+ silent_buf <= '0';
+ last_d <= (others => '0');
+ elsif rising_edge(clk) and sos = '1' then
last_d <= d;
if last_d = d then
if silence < silent_thresh then
@@ -68,36 +68,36 @@ begin
silent_buf <= '1';
end if;
else
- silence <= (others => '0');
+ silence <= (others => '0');
silent_buf <= '0';
end if;
end if;
end process;
- process (clk, sos, interval, valid_thresh,validity )
+ process (clk, sos, interval, valid_thresh, validity)
begin
if n_reset = '0' then
- validity <= (others => '0');
- valid_buf <= '0';
+ validity <= (others => '0');
+ valid_buf <= '0';
elsif rising_edge(clk) then
- if interval='1' then
-
- validity <= (others => '0');
- if validity > valid_thresh then
- valid_buf <='1';
- else
- valid_buf <='0';
- end if;
- elsif sos='1' then
- validity <= validity + 1;
- end if;
- end if;
- end process;
+ if interval = '1' then
+
+ validity <= (others => '0');
+ if validity > valid_thresh then
+ valid_buf <= '1';
+ else
+ valid_buf <= '0';
+ end if;
+ elsif sos = '1' then
+ validity <= validity + 1;
+ end if;
+ end if;
+ end process;
silent <= silent_buf;
- valid <= valid_buf;
+ valid <= valid_buf;
- dbg<=interval;
+ dbg <= interval;
end rtl;
diff --git a/spdif.qpf b/spdif.qpf
index f64db1f..6f7f061 100644
--- a/spdif.qpf
+++ b/spdif.qpf
@@ -1,30 +1,30 @@
-# -------------------------------------------------------------------------- #
+# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2012 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
-# -------------------------------------------------------------------------- #
+# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 12.0 Build 178 05/31/2012 SJ Web Edition
-# Date created = 21:48:38 September 12, 2013
+# Date created = 21 : 48 : 38 September 12, 2013
#
-# -------------------------------------------------------------------------- #
+# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "12.0"
-DATE = "21:48:38 September 12, 2013"
+ DATE = "21:48:38 September 12, 2013"
# Revisions
-PROJECT_REVISION = "spdif"
+ PROJECT_REVISION = "spdif"
diff --git a/spdif.qsf b/spdif.qsf
index e8889ac..12a4f19 100644
--- a/spdif.qsf
+++ b/spdif.qsf
@@ -1,58 +1,58 @@
#
set_global_assignment -name FAMILY "Cyclone II"
-set_global_assignment -name DEVICE EP2C5T144C8
-set_global_assignment -name TOP_LEVEL_ENTITY spdif
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:33:12 MAY 03, 2018"
-set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+ set_global_assignment -name DEVICE EP2C5T144C8
+ set_global_assignment -name TOP_LEVEL_ENTITY spdif
+ set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
+ set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:33:12 MAY 03, 2018"
+ set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_location_assignment PIN_3 -to n_leds[0]
-set_location_assignment PIN_7 -to n_leds[1]
-set_location_assignment PIN_9 -to n_leds[2]
-set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[0]
-set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[1]
-set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[2]
-set_location_assignment PIN_17 -to xtal_50mhz
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_location_assignment PIN_143 -to spdif_in
-set_location_assignment PIN_73 -to n_rst_in
+ set_location_assignment PIN_3 -to n_leds[0]
+ set_location_assignment PIN_7 -to n_leds[1]
+ set_location_assignment PIN_9 -to n_leds[2]
+ set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[0]
+ set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[1]
+ set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[2]
+ set_location_assignment PIN_17 -to xtal_50mhz
+ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+ set_location_assignment PIN_143 -to spdif_in
+ set_location_assignment PIN_73 -to n_rst_in
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to spdif_in
-set_location_assignment PIN_112 -to n_mute_out
-set_location_assignment PIN_114 -to n_stby_out
-set_global_assignment -name VHDL_FILE ccd.vhd
-set_global_assignment -name VHDL_FILE counter.vhd
-set_global_assignment -name VHDL_FILE dflipflop.vhd
-set_global_assignment -name VHDL_FILE pll100.vhd
-set_global_assignment -name VHDL_FILE pll200.vhd
-set_global_assignment -name VHDL_FILE spdif.vhd
-set_global_assignment -name VHDL_FILE bmc_decoder.vhd
-set_global_assignment -name VHDL_FILE spdif_decoder.vhd
-set_global_assignment -name VHDL_FILE silence_detector.vhd
-set_global_assignment -name VHDL_FILE detector.vhd
-set_global_assignment -name VHDL_FILE divider.vhd
-set_global_assignment -name SOURCE_FILE db/spdif.cmp.rdb
-set_global_assignment -name SDC_FILE spdif.sdc
+ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to spdif_in
+ set_location_assignment PIN_112 -to n_mute_out
+ set_location_assignment PIN_114 -to n_stby_out
+ set_global_assignment -name VHDL_FILE ccd.vhd
+ set_global_assignment -name VHDL_FILE counter.vhd
+ set_global_assignment -name VHDL_FILE dflipflop.vhd
+ set_global_assignment -name VHDL_FILE pll100.vhd
+ set_global_assignment -name VHDL_FILE pll200.vhd
+ set_global_assignment -name VHDL_FILE spdif.vhd
+ set_global_assignment -name VHDL_FILE bmc_decoder.vhd
+ set_global_assignment -name VHDL_FILE spdif_decoder.vhd
+ set_global_assignment -name VHDL_FILE silence_detector.vhd
+ set_global_assignment -name VHDL_FILE detector.vhd
+ set_global_assignment -name VHDL_FILE divider.vhd
+ set_global_assignment -name SOURCE_FILE db/spdif.cmp.rdb
+ set_global_assignment -name SDC_FILE spdif.sdc
-set_location_assignment PIN_41 -to dbg[0]
-set_location_assignment PIN_101 -to dbg[1]
-set_location_assignment PIN_103 -to dbg[2]
-set_location_assignment PIN_104 -to dbg[3]
-set_location_assignment PIN_113 -to dbg[4]
-set_location_assignment PIN_115 -to dbg[5]
-set_location_assignment PIN_118 -to dbg[6]
-set_location_assignment PIN_119 -to dbg[7]
-set_global_assignment -name USE_CONFIGURATION_DEVICE ON
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND"
+ set_location_assignment PIN_41 -to dbg[0]
+ set_location_assignment PIN_101 -to dbg[1]
+ set_location_assignment PIN_103 -to dbg[2]
+ set_location_assignment PIN_104 -to dbg[3]
+ set_location_assignment PIN_113 -to dbg[4]
+ set_location_assignment PIN_115 -to dbg[5]
+ set_location_assignment PIN_118 -to dbg[6]
+ set_location_assignment PIN_119 -to dbg[7]
+ set_global_assignment -name USE_CONFIGURATION_DEVICE on
+ set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+ set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND"
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+ set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
+ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
diff --git a/spdif.vhd b/spdif.vhd
index cf78f55..e3016a1 100644
--- a/spdif.vhd
+++ b/spdif.vhd
@@ -12,7 +12,7 @@ entity spdif is
n_leds : out std_logic_vector(2 downto 0);
n_mute_out : out std_logic;
n_stby_out : out std_logic;
- dbg : out std_logic_vector(7 downto 0)
+ dbg : out std_logic_vector(7 downto 0)
);
end spdif;
@@ -20,19 +20,19 @@ end spdif;
architecture rtl of spdif is
-component detector is
- port (
- clk_in : in std_logic;
- spdif_in: in std_logic;
- n_reset : in std_logic;
- divisor : in integer;
- silent_thresh : in integer;
- valid_divisor: in integer;
- valid_thresh : in integer;
- mute : out std_logic;
- dbg:out std_logic_vector(7 downto 0)
- );
-end component;
+ component detector is
+ port (
+ clk_in : in std_logic;
+ spdif_in : in std_logic;
+ n_reset : in std_logic;
+ divisor : in integer;
+ silent_thresh : in integer;
+ valid_divisor : in integer;
+ valid_thresh : in integer;
+ mute : out std_logic;
+ dbg : out std_logic_vector(7 downto 0)
+ );
+ end component;
component pll100 is
port (
@@ -61,7 +61,7 @@ end component;
signal mute1 : std_logic;
signal mute2 : std_logic;
signal mute3 : std_logic;
- signal mute : std_logic;
+ signal mute : std_logic;
begin
n_reset <= n_rst_in;
@@ -76,49 +76,49 @@ begin
-- 96000Hz
det1 : detector port map (
- n_reset => n_reset,
- clk_in => clk_200mhz,
- spdif_in => spdif_in,
+ n_reset => n_reset,
+ clk_in => clk_200mhz,
+ spdif_in => spdif_in,
- divisor => 2, -- divisor to turn clk_in into 6x spdif base frequency
- silent_thresh => 96000, -- number of samples of same sample before we declare silence
- valid_divisor => 100000000, -- (clk_in/(divisor*valid_divisor)) is period for validity checks
- valid_thresh => 90000, -- number of valid samples that must be received in validity period to declare it's all ok.
+ divisor => 2, -- divisor to turn clk_in into 6x spdif base frequency
+ silent_thresh => 96000, -- number of samples of same sample before we declare silence
+ valid_divisor => 100000000, -- (clk_in/(divisor*valid_divisor)) is period for validity checks
+ valid_thresh => 90000, -- number of valid samples that must be received in validity period to declare it's all ok.
- mute => mute1
+ mute => mute1
);
-- 44100Hz
det2 : detector port map (
- n_reset => n_reset,
- clk_in => clk_200mhz,
- spdif_in => spdif_in,
+ n_reset => n_reset,
+ clk_in => clk_200mhz,
+ spdif_in => spdif_in,
- divisor => 5, -- divisor to turn clk_in into 6x spdif base frequency
- silent_thresh => 44100, -- number of samples of same sample before we declare silence
- valid_divisor => 40000000, -- (clk_in/(divisor*valid_divisor)) is period for validity checks
- valid_thresh => 40000, -- number of valid samples that must be received in validity period to declare it's all ok.
+ divisor => 5, -- divisor to turn clk_in into 6x spdif base frequency
+ silent_thresh => 44100, -- number of samples of same sample before we declare silence
+ valid_divisor => 40000000, -- (clk_in/(divisor*valid_divisor)) is period for validity checks
+ valid_thresh => 40000, -- number of valid samples that must be received in validity period to declare it's all ok.
- mute => mute2,
- dbg => dbg
+ mute => mute2,
+ dbg => dbg
);
-- 32000Hz
det3 : detector port map (
- n_reset => n_reset,
- clk_in => clk_200mhz,
- spdif_in => spdif_in,
+ n_reset => n_reset,
+ clk_in => clk_200mhz,
+ spdif_in => spdif_in,
- divisor => 8, -- divisor to turn clk_in into 6x spdif base frequency
- silent_thresh => 32000, -- number of samples of same sample before we declare silence
- valid_divisor => 25000000, -- (clk_in/(divisor*valid_divisor)) is period for validity checks
- valid_thresh => 30000, -- number of valid samples that must be received in validity period to declare it's all ok.
+ divisor => 8, -- divisor to turn clk_in into 6x spdif base frequency
+ silent_thresh => 32000, -- number of samples of same sample before we declare silence
+ valid_divisor => 25000000, -- (clk_in/(divisor*valid_divisor)) is period for validity checks
+ valid_thresh => 30000, -- number of valid samples that must be received in validity period to declare it's all ok.
- mute => mute3
+ mute => mute3
);
-mute <= mute1 or mute2 or mute3;
+ mute <= mute1 or mute2 or mute3;
n_mute_out <= not mute;
n_stby_out <= not mute;
diff --git a/spdif_decoder.vhd b/spdif_decoder.vhd
index a8e9d94..c16a6f5 100644
--- a/spdif_decoder.vhd
+++ b/spdif_decoder.vhd
@@ -14,24 +14,24 @@ entity spdif_decoder is
);
-port (
- n_reset:in std_logic;
- spdif:in std_logic;
- clk:in std_logic;
-
- bmc_ready: out std_logic;
- bmc_e: out std_logic;
- bmc_l: out std_logic;
- bmc_d : out std_logic;
-
- d : out std_logic_vector(26 downto 0);
- ready: out std_logic;
- sof: out std_logic;
- bna: out std_logic;
- sos: out std_logic
-);
+ port (
+ n_reset : in std_logic;
+ spdif : in std_logic;
+ clk : in std_logic;
+
+ bmc_ready : out std_logic;
+ bmc_e : out std_logic;
+ bmc_l : out std_logic;
+ bmc_d : out std_logic;
+
+ d : out std_logic_vector(26 downto 0);
+ ready : out std_logic;
+ sof : out std_logic;
+ bna : out std_logic;
+ sos : out std_logic
+ );
end spdif_decoder;
-
+
architecture rtl of spdif_decoder is
@@ -100,7 +100,7 @@ begin
end process;
- parity_valid<= not xor_reduce(d_sr(31 downto 4));
+ parity_valid <= not xor_reduce(d_sr(31 downto 4));
process (clk, b_ready, e_sr, l_sr, d_sr, parity_valid, n_reset)
begin
@@ -114,30 +114,30 @@ begin
if (d_sr(3 downto 1) = "010") and (l_sr(3 downto 1) = "101") then --B code
d_buf <= d_sr(29 downto 3);
sof_buf <= '1';
- sos_buf <='1';
+ sos_buf <= '1';
bna_buf <= '0';
ready_buf <= '1';
elsif (d_sr(3 downto 1) = "100") and (l_sr(3 downto 1) = "011") then --M code
d_buf <= d_sr(29 downto 3);
sof_buf <= '0';
- sos_buf <='1';
+ sos_buf <= '1';
bna_buf <= '0';
ready_buf <= '1';
elsif (d_sr(3 downto 0) = "0100") and (l_sr(3 downto 0) = "0001") then --W code
d_buf <= d_sr(30 downto 4);
sof_buf <= '0';
- sos_buf <='0';
+ sos_buf <= '0';
bna_buf <= '1';
ready_buf <= '1';
else
- sof_buf <= '0';
- sos_buf <='0';
- bna_buf <= '1';
- ready_buf <= '0';
+ sof_buf <= '0';
+ sos_buf <= '0';
+ bna_buf <= '1';
+ ready_buf <= '0';
end if;
else
sof_buf <= '0';
- sos_buf <='0';
+ sos_buf <= '0';
bna_buf <= '1';
ready_buf <= '0';
end if;