diff options
Diffstat (limited to 'spdif.vhd')
| -rw-r--r-- | spdif.vhd | 82 |
1 files changed, 41 insertions, 41 deletions
@@ -12,7 +12,7 @@ entity spdif is n_leds : out std_logic_vector(2 downto 0); n_mute_out : out std_logic; n_stby_out : out std_logic; - dbg : out std_logic_vector(7 downto 0) + dbg : out std_logic_vector(7 downto 0) ); end spdif; @@ -20,19 +20,19 @@ end spdif; architecture rtl of spdif is -component detector is - port ( - clk_in : in std_logic; - spdif_in: in std_logic; - n_reset : in std_logic; - divisor : in integer; - silent_thresh : in integer; - valid_divisor: in integer; - valid_thresh : in integer; - mute : out std_logic; - dbg:out std_logic_vector(7 downto 0) - ); -end component; + component detector is + port ( + clk_in : in std_logic; + spdif_in : in std_logic; + n_reset : in std_logic; + divisor : in integer; + silent_thresh : in integer; + valid_divisor : in integer; + valid_thresh : in integer; + mute : out std_logic; + dbg : out std_logic_vector(7 downto 0) + ); + end component; component pll100 is port ( @@ -61,7 +61,7 @@ end component; signal mute1 : std_logic; signal mute2 : std_logic; signal mute3 : std_logic; - signal mute : std_logic; + signal mute : std_logic; begin n_reset <= n_rst_in; @@ -76,49 +76,49 @@ begin -- 96000Hz det1 : detector port map ( - n_reset => n_reset, - clk_in => clk_200mhz, - spdif_in => spdif_in, + n_reset => n_reset, + clk_in => clk_200mhz, + spdif_in => spdif_in, - divisor => 2, -- divisor to turn clk_in into 6x spdif base frequency - silent_thresh => 96000, -- number of samples of same sample before we declare silence - valid_divisor => 100000000, -- (clk_in/(divisor*valid_divisor)) is period for validity checks - valid_thresh => 90000, -- number of valid samples that must be received in validity period to declare it's all ok. + divisor => 2, -- divisor to turn clk_in into 6x spdif base frequency + silent_thresh => 96000, -- number of samples of same sample before we declare silence + valid_divisor => 100000000, -- (clk_in/(divisor*valid_divisor)) is period for validity checks + valid_thresh => 90000, -- number of valid samples that must be received in validity period to declare it's all ok. - mute => mute1 + mute => mute1 ); -- 44100Hz det2 : detector port map ( - n_reset => n_reset, - clk_in => clk_200mhz, - spdif_in => spdif_in, + n_reset => n_reset, + clk_in => clk_200mhz, + spdif_in => spdif_in, - divisor => 5, -- divisor to turn clk_in into 6x spdif base frequency - silent_thresh => 44100, -- number of samples of same sample before we declare silence - valid_divisor => 40000000, -- (clk_in/(divisor*valid_divisor)) is period for validity checks - valid_thresh => 40000, -- number of valid samples that must be received in validity period to declare it's all ok. + divisor => 5, -- divisor to turn clk_in into 6x spdif base frequency + silent_thresh => 44100, -- number of samples of same sample before we declare silence + valid_divisor => 40000000, -- (clk_in/(divisor*valid_divisor)) is period for validity checks + valid_thresh => 40000, -- number of valid samples that must be received in validity period to declare it's all ok. - mute => mute2, - dbg => dbg + mute => mute2, + dbg => dbg ); -- 32000Hz det3 : detector port map ( - n_reset => n_reset, - clk_in => clk_200mhz, - spdif_in => spdif_in, + n_reset => n_reset, + clk_in => clk_200mhz, + spdif_in => spdif_in, - divisor => 8, -- divisor to turn clk_in into 6x spdif base frequency - silent_thresh => 32000, -- number of samples of same sample before we declare silence - valid_divisor => 25000000, -- (clk_in/(divisor*valid_divisor)) is period for validity checks - valid_thresh => 30000, -- number of valid samples that must be received in validity period to declare it's all ok. + divisor => 8, -- divisor to turn clk_in into 6x spdif base frequency + silent_thresh => 32000, -- number of samples of same sample before we declare silence + valid_divisor => 25000000, -- (clk_in/(divisor*valid_divisor)) is period for validity checks + valid_thresh => 30000, -- number of valid samples that must be received in validity period to declare it's all ok. - mute => mute3 + mute => mute3 ); -mute <= mute1 or mute2 or mute3; + mute <= mute1 or mute2 or mute3; n_mute_out <= not mute; n_stby_out <= not mute; |