1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity silence_detector is
port
(
silent_thresh : in integer;
valid_thresh : in integer;
valid_divisor : in integer;
clk : in std_logic;
sos : in std_logic;
d : in std_logic_vector(23 downto 0);
n_reset : in std_logic;
silent : out std_logic;
valid : out std_logic;
dbg : out std_logic
);
end silence_detector;
architecture rtl of silence_detector is
component counter is
port
(
divisor : in integer;
clk : in std_logic;
n_reset : in std_logic;
pulse_out : out std_logic
);
end component;
signal silence : std_logic_vector (31 downto 0);
signal last_d : std_logic_vector (23 downto 0);
signal silent_buf : std_logic;
signal valid_buf : std_logic;
signal validity : std_logic_vector(31 downto 0);
signal interval : std_logic;
begin
vcnt : counter port map (
n_reset => n_reset,
clk => clk,
divisor => valid_divisor,
pulse_out =>interval
);
process (last_d, d, clk, sos, silent_thresh, silence)
begin
if n_reset = '0' then
silence <= (others => '0');
silent_buf <= '0';
last_d <= (others => '0');
elsif rising_edge(clk) and sos='1' then
last_d <= d;
if last_d = d then
if silence < silent_thresh then
silence <= silence +1;
else
silent_buf <= '1';
end if;
else
silence <= (others => '0');
silent_buf <= '0';
end if;
end if;
end process;
process (clk, sos, interval, valid_thresh,validity )
begin
if n_reset = '0' then
validity <= (others => '0');
valid_buf <= '0';
elsif rising_edge(clk) then
if interval='1' then
validity <= (others => '0');
if validity > valid_thresh then
valid_buf <='1';
else
valid_buf <='0';
end if;
elsif sos='1' then
validity <= validity + 1;
end if;
end if;
end process;
silent <= silent_buf;
valid <= valid_buf;
dbg<=interval;
end rtl;
|
