diff options
Diffstat (limited to 'spdif.qsf')
| -rw-r--r-- | spdif.qsf | 102 |
1 files changed, 51 insertions, 51 deletions
@@ -1,58 +1,58 @@ # set_global_assignment -name FAMILY "Cyclone II" -set_global_assignment -name DEVICE EP2C5T144C8 -set_global_assignment -name TOP_LEVEL_ENTITY spdif -set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:33:12 MAY 03, 2018" -set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + set_global_assignment -name DEVICE EP2C5T144C8 + set_global_assignment -name TOP_LEVEL_ENTITY spdif + set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" + set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:33:12 MAY 03, 2018" + set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" + set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 + set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 + set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 + set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top + set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top + set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_location_assignment PIN_3 -to n_leds[0] -set_location_assignment PIN_7 -to n_leds[1] -set_location_assignment PIN_9 -to n_leds[2] -set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[0] -set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[1] -set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[2] -set_location_assignment PIN_17 -to xtal_50mhz -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_location_assignment PIN_143 -to spdif_in -set_location_assignment PIN_73 -to n_rst_in + set_location_assignment PIN_3 -to n_leds[0] + set_location_assignment PIN_7 -to n_leds[1] + set_location_assignment PIN_9 -to n_leds[2] + set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[0] + set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[1] + set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[2] + set_location_assignment PIN_17 -to xtal_50mhz + set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" + set_location_assignment PIN_143 -to spdif_in + set_location_assignment PIN_73 -to n_rst_in -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to spdif_in -set_location_assignment PIN_112 -to n_mute_out -set_location_assignment PIN_114 -to n_stby_out -set_global_assignment -name VHDL_FILE ccd.vhd -set_global_assignment -name VHDL_FILE counter.vhd -set_global_assignment -name VHDL_FILE dflipflop.vhd -set_global_assignment -name VHDL_FILE pll100.vhd -set_global_assignment -name VHDL_FILE pll200.vhd -set_global_assignment -name VHDL_FILE spdif.vhd -set_global_assignment -name VHDL_FILE bmc_decoder.vhd -set_global_assignment -name VHDL_FILE spdif_decoder.vhd -set_global_assignment -name VHDL_FILE silence_detector.vhd -set_global_assignment -name VHDL_FILE detector.vhd -set_global_assignment -name VHDL_FILE divider.vhd -set_global_assignment -name SOURCE_FILE db/spdif.cmp.rdb -set_global_assignment -name SDC_FILE spdif.sdc + set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to spdif_in + set_location_assignment PIN_112 -to n_mute_out + set_location_assignment PIN_114 -to n_stby_out + set_global_assignment -name VHDL_FILE ccd.vhd + set_global_assignment -name VHDL_FILE counter.vhd + set_global_assignment -name VHDL_FILE dflipflop.vhd + set_global_assignment -name VHDL_FILE pll100.vhd + set_global_assignment -name VHDL_FILE pll200.vhd + set_global_assignment -name VHDL_FILE spdif.vhd + set_global_assignment -name VHDL_FILE bmc_decoder.vhd + set_global_assignment -name VHDL_FILE spdif_decoder.vhd + set_global_assignment -name VHDL_FILE silence_detector.vhd + set_global_assignment -name VHDL_FILE detector.vhd + set_global_assignment -name VHDL_FILE divider.vhd + set_global_assignment -name SOURCE_FILE db/spdif.cmp.rdb + set_global_assignment -name SDC_FILE spdif.sdc -set_location_assignment PIN_41 -to dbg[0] -set_location_assignment PIN_101 -to dbg[1] -set_location_assignment PIN_103 -to dbg[2] -set_location_assignment PIN_104 -to dbg[3] -set_location_assignment PIN_113 -to dbg[4] -set_location_assignment PIN_115 -to dbg[5] -set_location_assignment PIN_118 -to dbg[6] -set_location_assignment PIN_119 -to dbg[7] -set_global_assignment -name USE_CONFIGURATION_DEVICE ON -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND" + set_location_assignment PIN_41 -to dbg[0] + set_location_assignment PIN_101 -to dbg[1] + set_location_assignment PIN_103 -to dbg[2] + set_location_assignment PIN_104 -to dbg[3] + set_location_assignment PIN_113 -to dbg[4] + set_location_assignment PIN_115 -to dbg[5] + set_location_assignment PIN_118 -to dbg[6] + set_location_assignment PIN_119 -to dbg[7] + set_global_assignment -name USE_CONFIGURATION_DEVICE on + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND" -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation + set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" + set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation |