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* | | | Fix tribuf testEddie Hung2019-08-221-1/+1
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* | | | Fix commentsEddie Hung2019-08-228-10/+11
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* | | | Remove tech independent synthesisEddie Hung2019-08-229-16/+20
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* | | | Remove dffe instantationEddie Hung2019-08-221-7/+0
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* | | | Move $dffe to dffs.{v,ys}Eddie Hung2019-08-224-18/+41
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* | | | Make multiplier wider, do not do tech independent synthEddie Hung2019-08-222-8/+6
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* | | | Fix all comments from PRSergeyDegtyar2019-08-2120-160/+465
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* | | | Add temp directorySergeyDegtyar2019-08-211-0/+1
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* | | | Fix tests; Remove simulation;SergeyDegtyar2019-08-2026-519/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add -map and -assert options for equiv_opt; !!! '-assert' option was commented for the next tests (unproven $equiv cells was found): - dffs; - div_mod; - latches; - mul_pow; - Add design -load; - Remove simulations;
* | | | Add new tests for ice40 architectureSergeyDegtyar2019-08-2027-0/+900
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* | | proc_clean: fix order of switch insertion.whitequark2019-08-194-0/+35
| | | | | | | | | | | | Fixes #1268.
* | | Add *.sv to tests/simple_abc9/.gitignoreClifford Wolf2019-08-191-0/+1
| |/ |/| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge remote-tracking branch 'origin/master' into clifford/testfastEddie Hung2019-08-1832-29/+485
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| * \ Merge branch 'master' into eddie/pr1266_againwhitequark2019-08-1824-2/+453
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| | * \ Merge https://github.com/bogdanvuk/yosys into bogdanvuk/opt_shareEddie Hung2019-08-1623-0/+451
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| | | * | Fix wrong results when opt_share called before opt_cleanBogdan Vukobratovic2019-08-071-1/+0
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| | | * | Support various binary operators in opt_shareBogdan Vukobratovic2019-08-043-0/+126
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| | | * | Tabs to spaces in opt_share examplesBogdan Vukobratovic2019-08-0310-150/+150
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| | | * | Fix spacing in opt_share tests, change wording in opt_share helpBogdan Vukobratovic2019-08-0310-155/+150
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| | | * | Reimplement opt_share to work on $alu and $pmuxBogdan Vukobratovic2019-07-2820-17/+295
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| | | * | Implement opt_shareBogdan Vukobratovic2019-07-264-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pass identifies arithmetic operators that share an operand and whose results are used in mutually exclusive cases controlled by a multiplexer, and merges them together by multiplexing the other operands
| * | | | Revert "Merge pull request #1280 from ↵Eddie Hung2019-08-129-29/+34
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | YosysHQ/revert-1266-eddie/ice40_full_adder" This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f.
* | | | Removal of more `stat` calls from testsEddie Hung2019-08-183-26/+26
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* | | | Speed up "make test" and related cleanupsClifford Wolf2019-08-175-11/+21
| |/ / |/| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Do not use Verific in tests/various/write_gzip.ysClifford Wolf2019-08-161-2/+2
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge remote-tracking branch 'origin/master' into eddie/fix_1262Eddie Hung2019-08-119-34/+29
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| * | Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"David Shah2019-08-109-34/+29
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* | | Add $alu testsEddie Hung2019-08-091-0/+42
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* | | Add alumacc versions of opt_expr testsEddie Hung2019-08-091-0/+84
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* | | Add new $alu test, remove wreduceEddie Hung2019-08-091-11/+21
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* | | Cleanup some moreEddie Hung2019-08-091-12/+0
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* | | Simplify opt_expr tests using equiv_optEddie Hung2019-08-091-72/+23
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* | Remove dump callEddie Hung2019-08-071-1/+0
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* | Move tests/various/opt* into tests/opt/Eddie Hung2019-08-075-1/+1
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* | Remove ice40_unlut call, simply do equiv_opt on synth_ice40Eddie Hung2019-08-071-3/+1
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* | Add testcase from removed opt_ff.{v,ys}Eddie Hung2019-08-071-0/+32
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* | Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but runEddie Hung2019-08-072-24/+0
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* | Merge pull request #1213 from YosysHQ/eddie/wreduce_addClifford Wolf2019-08-072-0/+196
|\ \ | | | | | | wreduce/opt_expr: improve width reduction for $add and $sub cells
| * | Add signed opt_expr testsEddie Hung2019-08-061-0/+50
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| * | Add signed testEddie Hung2019-08-061-0/+26
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| * | Move LSB tests from wreduce to opt_exprEddie Hung2019-08-062-99/+101
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| * | Merge remote-tracking branch 'origin/master' into eddie/wreduce_addEddie Hung2019-08-064-0/+20
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| * | | Add another testEddie Hung2019-07-191-1/+24
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| * | | Add one more test with trimming Y_WIDTH of $subEddie Hung2019-07-191-11/+14
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| * | | Be more explicitEddie Hung2019-07-191-6/+29
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| * | | Add tests for sub tooEddie Hung2019-07-191-1/+48
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| * | | Add testEddie Hung2019-07-191-0/+22
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* | | Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnorClifford Wolf2019-08-071-1/+3
|\ \ \ | |_|/ |/| | Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
| * | Support explicit FIRRTL properties for better accommodation of ↵Jim Lawson2019-07-311-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | FIRRTL/Verilog semantic differences. Use FIRRTL spec vlaues for definition of FIRRTL widths. Added support for '$pos`, `$pow` and `$xnor` cells. Enable tests/simple/operators.v since all operators tested there are now supported. Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
* | | Add test for writing gzip-compressed filesDavid Shah2019-08-062-0/+18
|/ / | | | | | | Signed-off-by: David Shah <dave@ds0.me>
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