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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 15:38:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 15:38:43 -0700 |
| commit | 769c750c226cfde5efcd1f75940b25f51330d67b (patch) | |
| tree | de8011d0ed0353a7f4f5f920516b2e035b8b2b89 /tests | |
| parent | bfc7164af7bf64cb2fe5d00e87bbfead841a4dc2 (diff) | |
| download | yosys-769c750c226cfde5efcd1f75940b25f51330d67b.tar.gz yosys-769c750c226cfde5efcd1f75940b25f51330d67b.tar.bz2 yosys-769c750c226cfde5efcd1f75940b25f51330d67b.zip | |
Add signed test
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/wreduce.ys | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys index 7e4f1765a..4257292f5 100644 --- a/tests/various/wreduce.ys +++ b/tests/various/wreduce.ys @@ -20,3 +20,29 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +########## + +read_verilog <<EOT +module wreduce_sub_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o); + assign o = (j >>> 4) - i; +endmodule +EOT + +hierarchy -auto-top +proc +design -save gold + +opt_expr +wreduce + +dump +select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i + +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter |