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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-09 10:30:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-09 10:30:53 -0700 |
| commit | 8350dfb80906742068b8ee771d15f0741624fed0 (patch) | |
| tree | 824a29fc844bc73993dd4c304bcccce167ce0c20 /tests | |
| parent | 93001116011d46e50c0a24b0bd21c2f07746dc42 (diff) | |
| download | yosys-8350dfb80906742068b8ee771d15f0741624fed0.tar.gz yosys-8350dfb80906742068b8ee771d15f0741624fed0.tar.bz2 yosys-8350dfb80906742068b8ee771d15f0741624fed0.zip | |
Add alumacc versions of opt_expr tests
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/opt/opt_expr.ys | 84 |
1 files changed, 84 insertions, 0 deletions
diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index 96ab2f31a..9f5e845ca 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -12,6 +12,7 @@ select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i ########## +# alumacc version of above design -reset read_verilog <<EOT module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o); @@ -41,6 +42,22 @@ select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i ########## +# alumacc version of above +design -reset +read_verilog <<EOT +module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o); + assign o = (i << 4) + j; +endmodule +EOT + +alumacc +equiv_opt -assert opt_expr -fine +design -load postopt + +select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i + +########## + design -reset read_verilog <<EOT module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o); @@ -55,6 +72,23 @@ select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i ########## +# alumacc version of above +design -reset +read_verilog <<EOT +module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o); + assign o = j - (i << 4); +endmodule +EOT + +alumacc +equiv_opt -assert opt_expr -fine +design -load postopt + +dump +select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i + +########## + design -reset read_verilog <<EOT module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o); @@ -69,6 +103,22 @@ select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i ########## +# alumacc version of above +design -reset +read_verilog <<EOT +module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o); + assign o = j - (i << 4); +endmodule +EOT + +alumacc +equiv_opt -assert opt_expr -fine +design -load postopt + +select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i + +########## + design -reset read_verilog <<EOT module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o); @@ -83,6 +133,23 @@ select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i ########## +# alumacc version of above +design -reset +read_verilog <<EOT +module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o); + assign o = (i << 4) - j; +endmodule +EOT + +alumacc +opt_expr -fine +equiv_opt -assert opt_expr -fine +design -load postopt + +select -assert-count 1 t:$alu r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i + +########## + design -reset read_verilog <<EOT module opt_expr_sub_test4(input [3:0] i, output [8:0] o); @@ -95,3 +162,20 @@ equiv_opt -assert opt_expr -fine design -load postopt select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i + +########## + +# alumacc version of above +design -reset +read_verilog <<EOT +module opt_expr_sub_test4(input [3:0] i, output [8:0] o); + assign o = 5'b00010 - i; +endmodule +EOT + +wreduce +alumacc +equiv_opt -assert opt_expr -fine +design -load postopt + +select -assert-count 1 t:$alu r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i |