diff options
| author | Clifford Wolf <clifford@clifford.at> | 2019-08-07 12:31:32 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-07 12:31:32 +0200 |
| commit | 48f7682e32a3aead82b304c3d13fa47920e128c0 (patch) | |
| tree | f0fbd11b7948d1cece0add7d82f580216e4fa439 /tests | |
| parent | 4c49ddf36af217d0dfa7dbd9d7e24b4dbc388ba9 (diff) | |
| parent | 3b8c917025e1be9695468588082e9175e918c9e9 (diff) | |
| download | yosys-48f7682e32a3aead82b304c3d13fa47920e128c0.tar.gz yosys-48f7682e32a3aead82b304c3d13fa47920e128c0.tar.bz2 yosys-48f7682e32a3aead82b304c3d13fa47920e128c0.zip | |
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/simple/xfirrtl | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl index ba61a4476..10063d2c2 100644 --- a/tests/simple/xfirrtl +++ b/tests/simple/xfirrtl @@ -1,10 +1,12 @@ # This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures. arraycells.v inst id[0] of +defvalue.sv Initial value not supported dff_different_styles.v dff_init.v Initial value not supported generate.v combinational loop hierdefparam.v inst id[0] of i2c_master_tests.v $adff +implicit_ports.v not fully initialized macros.v drops modules mem2reg.v drops modules mem_arst.v $adff @@ -12,7 +14,6 @@ memory.v $adff multiplier.v inst id[0] of muxtree.v drops modules omsp_dbg_uart.v $adff -operators.v $pow partsel.v drops modules process.v drops modules realexpr.v drops modules @@ -23,5 +24,6 @@ specify.v no code (empty module generates error subbytes.v $adff task_func.v drops modules values.v combinational loop +wandwor.v Invalid connect to an expression that is not a reference or a WritePort. vloghammer.v combinational loop wreduce.v original verilog issues ( -x where x isn't declared signed) |