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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 21:33:56 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 21:33:56 -0700 |
| commit | d5e8c0e6d33de71493855eca72fcc454a67a6140 (patch) | |
| tree | 3f7822d6bdf2bcb38b2834ff1184e06357e575d5 /tests | |
| parent | 35bf509603904633e4bfd1d21aef834966378a90 (diff) | |
| download | yosys-d5e8c0e6d33de71493855eca72fcc454a67a6140.tar.gz yosys-d5e8c0e6d33de71493855eca72fcc454a67a6140.tar.bz2 yosys-d5e8c0e6d33de71493855eca72fcc454a67a6140.zip | |
Remove ice40_unlut call, simply do equiv_opt on synth_ice40
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/opt/opt_lut.ys | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys index 59b12c351..a9fccbb62 100644 --- a/tests/opt/opt_lut.ys +++ b/tests/opt/opt_lut.ys @@ -1,4 +1,2 @@ read_verilog opt_lut.v -synth_ice40 -ice40_unlut -equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 +equiv_opt -map +/ice40/cells_sim.v -assert synth_ice40 |