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* Merge pull request #2045 from YosysHQ/eddie/fix2042Eddie Hung2020-05-144-0/+93
|\ | | | | verilog: error if no direction given for task arguments, default to input in SV mode
| * test: add another testcase as per @nakengelhardtEddie Hung2020-05-141-0/+25
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| * tests: update/extend task argument testsEddie Hung2020-05-132-2/+35
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| * tests: add #2042 testcaseEddie Hung2020-05-111-0/+12
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| * Setup tests/verilog properlyEddie Hung2020-05-112-0/+23
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* | Merge pull request #2050 from YosysHQ/eddie/opt_clean_fixesClaire Wolf2020-05-141-0/+13
|\ \ | | | | | | opt_clean: remove (* init *) regardless of -purge, remove (* init *) when consistent with sigmap, clean to behave identically
| * | opt_clean: improve warning messageEddie Hung2020-05-141-1/+1
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| * | opt_clean: add init testEddie Hung2020-05-141-0/+13
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* | Merge pull request #2027 from YosysHQ/eddie/verilog_neg_uptoClaire Wolf2020-05-141-0/+4
|\ \ | |/ |/| ast: swap range regardless of range_left >= 0
| * techlibs/common: more robustness when *_WIDTH = 0Eddie Hung2020-05-051-1/+0
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| * test: add failing testEddie Hung2020-05-041-0/+5
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* | intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-071-0/+20
| | | | | | | | | | | | | | | | | | | | By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
* | Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-071-0/+46
|\ \ | | | | | | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
| * | Bugfix in partsel.v signed indices test casesClaire Wolf2020-05-021-2/+2
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | Add tests based on the test case from #1990Claire Wolf2020-05-021-0/+46
| | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | | Merge pull request #2028 from zachjs/masterEddie Hung2020-05-062-0/+17
|\ \ \ | | | | | | | | verilog: allow null gen-if then block
| * | | verilog: allow null gen-if then blockZachary Snow2020-05-062-0/+17
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* | | Merge pull request #2024 from YosysHQ/eddie/primitive_srcEddie Hung2020-05-051-0/+16
|\ \ \ | | | | | | | | verilog: set src attribute for primitives
| * | | tests: add tests for primitives' srcEddie Hung2020-05-041-0/+16
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* / / verilog: fix specify src attributeEddie Hung2020-05-041-0/+6
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* | Merge pull request #2014 from YosysHQ/claire/fixoptaluClaire Wolf2020-05-031-0/+12
|\ \ | | | | | | Fix the other "opt_expr -fine" bug introduced in 213a89558
| * | test: add test for #2014Eddie Hung2020-05-021-0/+12
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* / tests: aiger test for wire->start_offset != 0Eddie Hung2020-05-022-0/+41
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* Add testcase for #2010Eddie Hung2020-05-011-0/+10
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* intel_alm: work around a Quartus ICEDan Ravensloft2020-04-231-0/+12
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* tests: read +/xilinx/cell_sim.v before xilinx_dsp testEddie Hung2020-04-221-0/+1
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* test: ice40_dsp test to read +/ice40/cells_sim.v for default paramsEddie Hung2020-04-221-0/+1
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* xilinx: xilinx_dffopt to read cells_sim.v; fix testEddie Hung2020-04-221-13/+22
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* Merge pull request #1949 from YosysHQ/eddie/select_blackboxEddie Hung2020-04-221-0/+28
|\ | | | | select: do not select inside black-/white- boxes unless '=' prefix used
| * tests: update select black/white-box testsEddie Hung2020-04-221-0/+7
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| * select: add test for not selecting inside black/white boxesEddie Hung2020-04-161-0/+21
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* | Merge pull request #1973 from YosysHQ/eddie/fix1966Eddie Hung2020-04-221-1/+3
|\ \ | | | | | | tests: fix various/plugin.sh when PREFIX != /usr/local/share
| * | tests: use `yosys-config --datdir` instead of hard-codedEddie Hung2020-04-221-1/+3
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* | | Merge pull request #1950 from YosysHQ/eddie/design_importEddie Hung2020-04-222-5/+22
|\ \ \ | | | | | | | | design: -import to not count black/white-boxes as candidates for top
| * | | design: add testEddie Hung2020-04-162-5/+22
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* | | Merge pull request #1976 from YosysHQ/dave/fix-sim-constClaire Wolf2020-04-221-0/+13
|\ \ \ | | | | | | | | sim: Fix handling of constant-connected cell inputs at startup
| * | | sim: Fix handling of constant-connected cell inputs at startupDavid Shah2020-04-211-0/+13
| | |/ | |/| | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | hierarchy: Convert positional parameters to named.Marcelina Kościelnicka2020-04-211-0/+23
| | | | | | | | | | | | Fixes #1821.
* | | Merge pull request #1851 from YosysHQ/claire/bitselwriteClaire Wolf2020-04-2113-0/+1224
|\ \ \ | | | | | | | | Improved rewrite code for writing to bit slice
| * | | Remove '-ignore_unknown_cells' option from 'sat'Eddie Hung2020-04-201-6/+6
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| * | | Simplify test case scriptEddie Hung2020-04-201-30/+17
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| * | | Remove ununsed filesEddie Hung2020-04-205-83/+0
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| * | | Modifications of tests as per Eddie's requestdiego2020-04-2015-78/+1237
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| * | | Wrong fixed valuediego2020-04-171-1/+1
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| * | | Adding tests for dynamic part select optimisationdiego2020-04-167-0/+161
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* | | | tests: remove write_ilangEddie Hung2020-04-202-3/+0
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* | | | abc9: add testcase reduced from #1970Eddie Hung2020-04-201-0/+19
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* | | tests: add select -unset testsEddie Hung2020-04-162-0/+20
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* | tests: add design -delete testsEddie Hung2020-04-162-0/+18
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* | Merge pull request #1943 from YosysHQ/dave/fix-1919David Shah2020-04-161-0/+18
|\ \ | | | | | | ast: Fix handling of identifiers in the global scope
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