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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-01 14:07:33 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-01 14:07:33 -0700 |
| commit | 7f9ecddb7f868a083ace6c82f97d80c2dd72dd29 (patch) | |
| tree | 2ff15c9af52415713e2d00f8f2e1beab64bb37db /tests | |
| parent | 8ee32adac324ff9bb705feddfa5e13089fc2801a (diff) | |
| download | yosys-7f9ecddb7f868a083ace6c82f97d80c2dd72dd29.tar.gz yosys-7f9ecddb7f868a083ace6c82f97d80c2dd72dd29.tar.bz2 yosys-7f9ecddb7f868a083ace6c82f97d80c2dd72dd29.zip | |
Add testcase for #2010
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/opt/bug2010.ys | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/opt/bug2010.ys b/tests/opt/bug2010.ys new file mode 100644 index 000000000..cef820867 --- /dev/null +++ b/tests/opt/bug2010.ys @@ -0,0 +1,10 @@ +read_verilog <<EOT +module test ( + input signed [1:0] n, + output [3:0] dout +); + assign dout = n + 4'sd 4; +endmodule +EOT + +equiv_opt -assert opt -fine |