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authorDan Ravensloft <dan.ravensloft@gmail.com>2020-04-16 12:24:04 +0100
committerMarcelina Koƛcielnicka <mwk@0x04.net>2020-05-07 21:03:13 +0200
commit5b779f7f4ef0bf2c4ad3a412da24fad30b078626 (patch)
treecb0fcd56575efe8a846fbd6a2888aee80998f644 /tests
parent06104249406972de01d0360df63a32cafcdf2ec5 (diff)
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intel_alm: direct LUTRAM cell instantiation
By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
Diffstat (limited to 'tests')
-rw-r--r--tests/arch/intel_alm/lutram.ys20
1 files changed, 20 insertions, 0 deletions
diff --git a/tests/arch/intel_alm/lutram.ys b/tests/arch/intel_alm/lutram.ys
new file mode 100644
index 000000000..6f997b67b
--- /dev/null
+++ b/tests/arch/intel_alm/lutram.ys
@@ -0,0 +1,20 @@
+read_verilog ../common/lutram.v
+hierarchy -top lutram_1w1r
+proc
+memory -nomap
+equiv_opt -run :prove -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/dff_sim.v -map +/intel_alm/common/mem_sim.v synth_intel_alm -family cyclonev -nobram
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd lutram_1w1r
+select -assert-count 16 t:MISTRAL_MLAB
+select -assert-count 1 t:MISTRAL_NOT
+select -assert-count 2 t:MISTRAL_ALUT2
+select -assert-count 8 t:MISTRAL_ALUT3
+select -assert-count 17 t:MISTRAL_FF
+select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_FF t:MISTRAL_MLAB %% t:* %D
+