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authorEddie Hung <eddie@fpgeh.com>2020-05-14 09:45:54 -0700
committerGitHub <noreply@github.com>2020-05-14 09:45:54 -0700
commit5bcde7ccc331e575682823222c97cc414bb3d808 (patch)
tree07405fdd0d0652ad75bb881ef67fa66a5e3315a3 /tests
parentf02e20907e5d0f343c83ed1a762a39299105167e (diff)
parent56a5b1d2daf1b244990d81f32183034071ebd185 (diff)
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Merge pull request #2045 from YosysHQ/eddie/fix2042
verilog: error if no direction given for task arguments, default to input in SV mode
Diffstat (limited to 'tests')
-rw-r--r--tests/verilog/.gitignore3
-rw-r--r--tests/verilog/bug2042-sv.ys59
-rw-r--r--tests/verilog/bug2042.ys11
-rwxr-xr-xtests/verilog/run-test.sh20
4 files changed, 93 insertions, 0 deletions
diff --git a/tests/verilog/.gitignore b/tests/verilog/.gitignore
new file mode 100644
index 000000000..b48f808a1
--- /dev/null
+++ b/tests/verilog/.gitignore
@@ -0,0 +1,3 @@
+/*.log
+/*.out
+/run-test.mk
diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys
new file mode 100644
index 000000000..e815d7fc5
--- /dev/null
+++ b/tests/verilog/bug2042-sv.ys
@@ -0,0 +1,59 @@
+read_verilog -sv <<EOT
+module Task_Test_Top
+(
+input a,
+output b
+);
+
+ task SomeTaskName(a);
+ b = ~a;
+ endtask
+
+ always @*
+ SomeTaskName(a);
+
+ assert property (b == ~a);
+
+endmodule
+EOT
+proc
+sat -verify -prove-asserts
+
+
+design -reset
+read_verilog -sv <<EOT
+module Task_Test_Top
+(
+input a,
+output b, c
+);
+
+ task SomeTaskName(x, output y, z);
+ y = ~x;
+ z = x;
+ endtask
+
+ always @*
+ SomeTaskName(a, b, c);
+
+ assert property (b == ~a);
+ assert property (c == a);
+
+endmodule
+EOT
+proc
+sat -verify -prove-asserts
+
+
+design -reset
+logger -expect error "syntax error, unexpected TOK_ENDTASK, expecting ';'" 1
+read_verilog -sv <<EOT
+module Task_Test_Top
+(
+);
+
+ task SomeTaskName(a)
+ endtask
+
+endmodule
+EOT
diff --git a/tests/verilog/bug2042.ys b/tests/verilog/bug2042.ys
new file mode 100644
index 000000000..f9d8e2837
--- /dev/null
+++ b/tests/verilog/bug2042.ys
@@ -0,0 +1,11 @@
+logger -expect error "task/function argument direction missing" 1
+read_verilog <<EOT
+module Task_Test_Top
+(
+);
+
+ task SomeTaskName(a)
+ endtask
+
+endmodule
+EOT
diff --git a/tests/verilog/run-test.sh b/tests/verilog/run-test.sh
new file mode 100755
index 000000000..ea56b70f0
--- /dev/null
+++ b/tests/verilog/run-test.sh
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+ echo "all:: run-$x"
+ echo "run-$x:"
+ echo " @echo 'Running $x..'"
+ echo " @../../yosys -ql ${x%.ys}.log $x"
+done
+for s in *.sh; do
+ if [ "$s" != "run-test.sh" ]; then
+ echo "all:: run-$s"
+ echo "run-$s:"
+ echo " @echo 'Running $s..'"
+ echo " @bash $s"
+ fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk