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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-06 12:10:28 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-06 12:10:28 -0700 |
| commit | a299e606f864942c7edf90c4ad3998f4f4a346cf (patch) | |
| tree | 2150af3a69a0bb174f0a53139e606b5d3ed7b803 /tests | |
| parent | 283b1130a651324ff870059dc3b1cf869948db93 (diff) | |
| parent | 8f9bba1bbfdb56630dadd75a3f92f7bfb26b3df6 (diff) | |
| download | yosys-a299e606f864942c7edf90c4ad3998f4f4a346cf.tar.gz yosys-a299e606f864942c7edf90c4ad3998f4f4a346cf.tar.bz2 yosys-a299e606f864942c7edf90c4ad3998f4f4a346cf.zip | |
Merge pull request #2028 from zachjs/master
verilog: allow null gen-if then block
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/gen_if_null.v | 13 | ||||
| -rw-r--r-- | tests/various/gen_if_null.ys | 4 |
2 files changed, 17 insertions, 0 deletions
diff --git a/tests/various/gen_if_null.v b/tests/various/gen_if_null.v new file mode 100644 index 000000000..a12ac6288 --- /dev/null +++ b/tests/various/gen_if_null.v @@ -0,0 +1,13 @@ +module test(x, y, z); + localparam OFF = 0; + generate + if (OFF) ; + else input x; + if (!OFF) input y; + else ; + if (OFF) ; + else ; + if (OFF) ; + input z; + endgenerate +endmodule diff --git a/tests/various/gen_if_null.ys b/tests/various/gen_if_null.ys new file mode 100644 index 000000000..31dfc444b --- /dev/null +++ b/tests/various/gen_if_null.ys @@ -0,0 +1,4 @@ +read_verilog gen_if_null.v +select -assert-count 1 test/x +select -assert-count 1 test/y +select -assert-count 1 test/z |