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* verilog: Fix const eval of unbased unsized constantsJannis Harder2023-04-202-0/+35
| | | | | | | | | | | | | | When the verilog frontend perfomed constant evaluation of unbased unsized constants in a context-determined expression it did not properly extend them by repeating the bit value. This only affected constant evaluation and not constants that made it through unchanged to RTLIL. The latter case was already covered by tests and working before. This fixes the const-eval issue by checking the `is_unsized` flag in bitsAsConst and extending the value accordingly. The newly added test also tests the already working non-const-eval case to highlight that both cases should behave the same.
* verilog: Support void functionsJannis Harder2023-03-201-0/+37
| | | | | | | The difference between void functions and tasks is that always_comb's implicit sensitivity list behaves as if functions were inlined, but ignores signals read only in tasks. This only matters for event based simulation, and for synthesis we can treat a void function like a task.
* Add test for typenames using constants shadowed later onZachary Snow2023-02-122-0/+16
| | | | | This possible edge case came up while reviewing #3555. It is currently handled correctly, but there is no clear test coverage.
* verilog: fix width/sign detection for functionsZachary Snow2022-05-302-0/+46
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* verilog: fix size and signedness of array querying functionsJannis Harder2022-05-301-0/+52
| | | | | | | | | | genrtlil.cc and simplify.cc had inconsistent and slightly broken handling of signedness for array querying functions. These functions are defined to return a signed result. Simplify always produced an unsigned and genrtlil always a signed 32-bit result ignoring the context. Includes tests for the the relvant edge cases for context dependent conversions.
* verilog: fix $past's signednessJannis Harder2022-05-251-0/+35
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* verilog: fix signedness when removing unreachable casesJannis Harder2022-05-241-0/+33
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* sv: fix always_comb auto nosync for nested and function blocksZachary Snow2022-04-052-0/+30
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* verilog: support for time scale delay valuesZachary Snow2022-02-141-0/+25
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* Fix access to whole sub-structs (#3086)Kamil Rakoczy2022-02-141-3/+2
| | | | | | * Add support for accessing whole struct * Update tests Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: fix dynamic dynamic range asgn elabZachary Snow2022-02-112-0/+108
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* verilog: fix const func eval with upto variablesZachary Snow2022-02-112-0/+84
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* sv: auto add nosync to certain always_comb local varsZachary Snow2022-01-078-0/+135
| | | | | If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
* sv: fix size cast internal expression extensionZachary Snow2022-01-072-0/+145
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* fixup verilog doubleslash testZachary Snow2022-01-032-0/+3
| | | | | - add generated doubleslash.v to .gitignore - ensure backend verilog can be read again
* preprocessor: do not destroy double slash escaped identifiersThomas Sailer2021-12-151-0/+19
| | | | | | | | | | | The preprocessor currently destroys double slash containing escaped identifiers (for example \a//b ). This is due to next_token trying to convert single line comments (//) into /* */ comments. This then leads to an unintuitive error message like this: ERROR: syntax error, unexpected '*' This patch fixes the error by recognizing escaped identifiers and returning them as single token. It also adds a testcase.
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-252-0/+37
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* sv: support wand and wor of data typesZachary Snow2021-09-212-0/+39
| | | | | | This enables the usage of declarations of wand or wor with a base type of logic, integer, or a typename. Note that declarations of nets with 2-state base types is still permitted, in violation of the spec.
* verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-212-0/+100
| | | | | | | | - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes
* sv: support declaration in generate for initializationZachary Snow2021-08-318-0/+114
| | | | | | | | This is accomplished by generating a unique name for the genvar, renaming references to the genvar only in the loop's initialization, guard, and incrementation, and finally adding a localparam inside the loop body with the original name so that the genvar can be shadowed as expected.
* sv: support declaration in procedural for initializationZachary Snow2021-08-304-0/+56
| | | | | In line with other tools, this adds an extra wrapping block around such for loops to appropriately scope the variable.
* verilog: save and restore overwritten macro argumentsZachary Snow2021-07-282-0/+23
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* sv: fix two struct access bugsZachary Snow2021-07-152-0/+92
| | | | | - preserve signedness of struct members - fix initial width detection of struct members (e.g., in case expressions)
* sv: fix up end label checkingZachary Snow2021-06-165-0/+51
| | | | | | | - disallow [gen]blocks with an end label but not begin label - check validity of module end label - fix memory leak of package name and end label - fix memory leak of module end label
* mem2reg: tolerate out of bounds constant accessesZachary Snow2021-06-082-0/+33
| | | | This brings the mem2reg behavior in line with the nomem2reg behavior.
* sv: support tasks and functions within packagesZachary Snow2021-06-012-0/+34
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* sv: check validity of package end labelZachary Snow2021-05-101-0/+15
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* preproc: test coverage for #2712Zachary Snow2021-03-303-0/+18
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* sv: allow typenames as function return typesZachary Snow2021-03-192-0/+40
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* sv: carry over global typedefs from previous filesZachary Snow2021-03-172-0/+60
| | | | | | | This breaks the ability to use a global typename as a standard identifier in a subsequent input file. This is otherwise backwards compatible, including for sources which previously included conflicting typedefs in each input file.
* sv: allow globals in one file to depend on globals in anotherZachary Snow2021-03-121-0/+20
| | | | | | This defers the simplification of globals so that globals in one file may depend on globals in other files. Adds a simplify() call downstream because globals are appended at the end.
* verilog: disallow overriding global parametersZachary Snow2021-03-111-0/+16
| | | | | | It was previously possible to override global parameters on a per-instance basis. This could be dangerous when using positional parameter bindings, hiding oversupplied parameters.
* Merge pull request #2626 from zachjs/param-no-defaultwhitequark2021-03-0710-0/+177
|\ | | | | sv: support for parameters without default values
| * sv: support for parameters without default valuesZachary Snow2021-03-0210-0/+177
| | | | | | | | | | | | | | | | | | - Modules with a parameter without a default value will be automatically deferred until the hierarchy pass - Allows for parameters without defaults as module items, rather than just int the `parameter_port_list`, despite being forbidden in the LRM - Check for parameters without defaults that haven't been overriden - Add location info to parameter/localparam declarations
* | Merge pull request #2632 from zachjs/width-limitwhitequark2021-03-072-0/+33
|\ \ | | | | | | verilog: impose limit on maximum expression width
| * | verilog: impose limit on maximum expression widthZachary Snow2021-03-042-0/+33
| |/ | | | | | | | | Designs with unreasonably wide expressions would previously get stuck allocating memory forever.
* / sv: fix some edge cases for unbased unsized literalsZachary Snow2021-03-062-0/+47
|/ | | | | | - Fix explicit size cast of unbased unsized literals - Fix unbased unsized literal bound directly to port - Output `is_unsized` flag in `dumpAst`
* verilog: fix sizing of ports with int types in module headersZachary Snow2021-03-012-0/+61
| | | | | | Declaring the ports as standard module items already worked as expected. This adds a missing usage of `checkRange()` so that headers such as `module m(output integer x);` now work correctly.
* verilog: fix handling of nested ifdef directivesZachary Snow2021-03-015-0/+50
| | | | | - track depth so we know whether to consider higher-level elsifs - error on unmatched endif/elsif/else
* Merge pull request #2615 from zachjs/genrtlil-conflictwhitequark2021-03-016-0/+56
|\ | | | | genrtlil: improve name conflict error messaging
| * genrtlil: improve name conflict error messagingZachary Snow2021-02-266-0/+56
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* | sv: extended support for integer typesZachary Snow2021-02-284-0/+78
|/ | | | | | | | | - Standard data declarations can now use any integer type - Parameters and localparams can now use any integer type - Function returns types can now use any integer type - Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits) - Added longint type (64 bits) - Unified parser source for integer type widths
* Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and ↵TimRudy2021-02-242-0/+438
| | | | turn-off (#2566)
* Merge pull request #2594 from zachjs/func-arg-widthwhitequark2021-02-234-0/+48
|\ | | | | verilog: fix sizing of constant args for tasks/functions
| * verilog: fix sizing of constant args for tasks/functionsZachary Snow2021-02-214-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases
* | verilog: error on macro invocations with missing argument listsZachary Snow2021-02-192-0/+22
|/ | | | | | This would previously complain about an undefined internal macro if the unapplied macro had not already been used. If it had, it would incorrectly use the arguments from the previous invocation.
* Merge pull request #2578 from zachjs/genblk-portZachary Snow2021-02-111-0/+12
|\ | | | | verlog: allow shadowing module ports within generate blocks
| * verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-071-0/+12
| | | | | | | | | | | | | | | | This is a somewhat obscure edge case I encountered while working on test cases for earlier changes. Declarations in generate blocks should not be checked against the list of ports. This change also adds a check forbidding declarations within generate blocks being tagged as inputs or outputs.
* | Add missing is_signed to type_atomKamil Rakoczy2021-02-111-0/+19
|/ | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Add check of begin/end labels for genblockKamil Rakoczy2021-02-041-0/+26
| | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
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