verilog: fix handling of nested ifdef directives

- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else

5 files changed, 50 insertions, 0 deletions

diff --git a/tests/verilog/include_self.v b/tests/verilog/include_self.v
new file mode 100644
index 000000000..23ffc7104
--- /dev/null
+++ b/tests/verilog/include_self.v
@@ -0,0 +1,30 @@
+`ifdef GUARD_5
+module top;
+	wire x;
+endmodule
+
+`elsif GUARD_4
+`define GUARD_5
+`include "include_self.v"
+
+`elsif GUARD_3
+`define GUARD_4
+`include "include_self.v"
+
+`elsif GUARD_2
+`define GUARD_3
+`include "include_self.v"
+
+`elsif GUARD_1
+`define GUARD_2
+`include "include_self.v"
+
+`elsif GUARD_0
+`define GUARD_1
+`include "include_self.v"
+
+`else
+`define GUARD_0
+`include "include_self.v"
+
+`endif
diff --git a/tests/verilog/include_self.ys b/tests/verilog/include_self.ys
new file mode 100644
index 000000000..07d840d68
--- /dev/null
+++ b/tests/verilog/include_self.ys
@@ -0,0 +1,2 @@
+read_verilog include_self.v
+select -assert-count 1 top/x
diff --git a/tests/verilog/unmatched_else.ys b/tests/verilog/unmatched_else.ys
new file mode 100644
index 000000000..413f413c3
--- /dev/null
+++ b/tests/verilog/unmatched_else.ys
@@ -0,0 +1,6 @@
+logger -expect error "Found `else outside of macro conditional branch!" 1
+read_verilog <<EOT
+module top;
+`else
+endmodule
+EOT
diff --git a/tests/verilog/unmatched_elsif.ys b/tests/verilog/unmatched_elsif.ys
new file mode 100644
index 000000000..e0ed0aa49
--- /dev/null
+++ b/tests/verilog/unmatched_elsif.ys
@@ -0,0 +1,6 @@
+logger -expect error "Found `elsif outside of macro conditional branch!" 1
+read_verilog <<EOT
+module top;
+`elsif
+endmodule
+EOT
diff --git a/tests/verilog/unmatched_endif.ys b/tests/verilog/unmatched_endif.ys
new file mode 100644
index 000000000..39d60381d
--- /dev/null
+++ b/tests/verilog/unmatched_endif.ys
@@ -0,0 +1,6 @@
+logger -expect error "Found `endif outside of macro conditional branch!" 1
+read_verilog <<EOT
+module top;
+`endif
+endmodule
+EOT