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| author | Zachary Snow <zach@zachjs.com> | 2021-03-04 15:08:16 -0500 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2021-03-04 15:20:52 -0500 |
| commit | c18ddbcd822410095d28c4be1c3ac3c6358622d2 (patch) | |
| tree | 405d9312fc0b723f0af7b730bece916fde66fc1a /tests/verilog | |
| parent | 7d2097b00538fa366cc433b23c2c307db0e3a4be (diff) | |
| download | yosys-c18ddbcd822410095d28c4be1c3ac3c6358622d2.tar.gz yosys-c18ddbcd822410095d28c4be1c3ac3c6358622d2.tar.bz2 yosys-c18ddbcd822410095d28c4be1c3ac3c6358622d2.zip | |
verilog: impose limit on maximum expression width
Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.
Diffstat (limited to 'tests/verilog')
| -rw-r--r-- | tests/verilog/absurd_width.ys | 17 | ||||
| -rw-r--r-- | tests/verilog/absurd_width_const.ys | 16 |
2 files changed, 33 insertions, 0 deletions
diff --git a/tests/verilog/absurd_width.ys b/tests/verilog/absurd_width.ys new file mode 100644 index 000000000..c0d2af4c2 --- /dev/null +++ b/tests/verilog/absurd_width.ys @@ -0,0 +1,17 @@ +logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1 +read_verilog <<EOF +module top( + input inp, + output out +); + assign out = + {1024 { + {1024 { + {1024 { + inp + }} + }} + }} + ; +endmodule +EOF diff --git a/tests/verilog/absurd_width_const.ys b/tests/verilog/absurd_width_const.ys new file mode 100644 index 000000000..b7191fd0d --- /dev/null +++ b/tests/verilog/absurd_width_const.ys @@ -0,0 +1,16 @@ +logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1 +read_verilog <<EOF +module top( + output out +); + assign out = + {1024 { + {1024 { + {1024 { + 1'b1 + }} + }} + }} + ; +endmodule +EOF |