diff options
| author | Kamil Rakoczy <krakoczy@antmicro.com> | 2022-02-14 14:34:20 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-14 14:34:20 +0100 |
| commit | 68c67c40ec75b192f4f1be9711afe0df8973e797 (patch) | |
| tree | f67834903e40ae61b39a04555ff1b96763c59cd0 /tests/verilog | |
| parent | 59738c09beb3ba43a693b77eb4545122a99df7d2 (diff) | |
| download | yosys-68c67c40ec75b192f4f1be9711afe0df8973e797.tar.gz yosys-68c67c40ec75b192f4f1be9711afe0df8973e797.tar.bz2 yosys-68c67c40ec75b192f4f1be9711afe0df8973e797.zip | |
Fix access to whole sub-structs (#3086)
* Add support for accessing whole struct
* Update tests
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
Diffstat (limited to 'tests/verilog')
| -rw-r--r-- | tests/verilog/struct_access.sv | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/tests/verilog/struct_access.sv b/tests/verilog/struct_access.sv index f13b8dd51..bc91e3f01 100644 --- a/tests/verilog/struct_access.sv +++ b/tests/verilog/struct_access.sv @@ -77,9 +77,8 @@ module top; `CHECK(s.y.a, 1, 0) `CHECK(s.y.b, 1, 1) - // TODO(zachjs): support access to whole sub-structs and unions - // `CHECK(s.x, 2, 0) - // `CHECK(s.y, 2, 1) + `CHECK(s.x, 2, 0) + `CHECK(s.y, 2, 1) assert (fail === 0); end |