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| author | Jannis Harder <me@jix.one> | 2022-05-24 17:18:53 +0200 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2022-05-25 16:32:08 -0400 |
| commit | b75fa62e9b2a9f4410084fb1c80ceb23ed9d9c48 (patch) | |
| tree | 3b14fe3f5d0ace0370c49b56d77fb9b2ee458f80 /tests/verilog | |
| parent | 63c9c9be5c0b0cc2b7f4588f1ac8e72eabc6bd0a (diff) | |
| download | yosys-b75fa62e9b2a9f4410084fb1c80ceb23ed9d9c48.tar.gz yosys-b75fa62e9b2a9f4410084fb1c80ceb23ed9d9c48.tar.bz2 yosys-b75fa62e9b2a9f4410084fb1c80ceb23ed9d9c48.zip | |
verilog: fix $past's signedness
Diffstat (limited to 'tests/verilog')
| -rw-r--r-- | tests/verilog/past_signedness.ys | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/tests/verilog/past_signedness.ys b/tests/verilog/past_signedness.ys new file mode 100644 index 000000000..91f32328b --- /dev/null +++ b/tests/verilog/past_signedness.ys @@ -0,0 +1,35 @@ +logger -expect-no-warnings + +read_verilog -formal <<EOT +module top(input clk); + reg signed [3:0] value = -1; + reg ready = 0; + + always @(posedge clk) begin + if (ready) + assert ($past(value) == -1); + ready <= 1; + end +endmodule +EOT + +prep -top top +sim -n 3 -clock clk + +design -reset + +read_verilog -formal <<EOT +module top(input clk); + reg signed [3:0] value = -1; + reg ready = 0; + + always @(posedge clk) begin + if (ready) + assert ($past(value + 4'b0000) == 15); + ready <= 1; + end +endmodule +EOT + +prep -top top +sim -n 3 -clock clk |