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* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-252-0/+37
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* sv: support wand and wor of data typesZachary Snow2021-09-212-0/+39
| | | | | | This enables the usage of declarations of wand or wor with a base type of logic, integer, or a typename. Note that declarations of nets with 2-state base types is still permitted, in violation of the spec.
* verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-212-0/+100
| | | | | | | | - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes
* sv: support declaration in generate for initializationZachary Snow2021-08-318-0/+114
| | | | | | | | This is accomplished by generating a unique name for the genvar, renaming references to the genvar only in the loop's initialization, guard, and incrementation, and finally adding a localparam inside the loop body with the original name so that the genvar can be shadowed as expected.
* sv: support declaration in procedural for initializationZachary Snow2021-08-304-0/+56
| | | | | In line with other tools, this adds an extra wrapping block around such for loops to appropriately scope the variable.
* verilog: save and restore overwritten macro argumentsZachary Snow2021-07-282-0/+23
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* sv: fix two struct access bugsZachary Snow2021-07-152-0/+92
| | | | | - preserve signedness of struct members - fix initial width detection of struct members (e.g., in case expressions)
* sv: fix up end label checkingZachary Snow2021-06-165-0/+51
| | | | | | | - disallow [gen]blocks with an end label but not begin label - check validity of module end label - fix memory leak of package name and end label - fix memory leak of module end label
* mem2reg: tolerate out of bounds constant accessesZachary Snow2021-06-082-0/+33
| | | | This brings the mem2reg behavior in line with the nomem2reg behavior.
* sv: support tasks and functions within packagesZachary Snow2021-06-012-0/+34
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* sv: check validity of package end labelZachary Snow2021-05-101-0/+15
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* preproc: test coverage for #2712Zachary Snow2021-03-303-0/+18
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* sv: allow typenames as function return typesZachary Snow2021-03-192-0/+40
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* sv: carry over global typedefs from previous filesZachary Snow2021-03-172-0/+60
| | | | | | | This breaks the ability to use a global typename as a standard identifier in a subsequent input file. This is otherwise backwards compatible, including for sources which previously included conflicting typedefs in each input file.
* sv: allow globals in one file to depend on globals in anotherZachary Snow2021-03-121-0/+20
| | | | | | This defers the simplification of globals so that globals in one file may depend on globals in other files. Adds a simplify() call downstream because globals are appended at the end.
* verilog: disallow overriding global parametersZachary Snow2021-03-111-0/+16
| | | | | | It was previously possible to override global parameters on a per-instance basis. This could be dangerous when using positional parameter bindings, hiding oversupplied parameters.
* Merge pull request #2626 from zachjs/param-no-defaultwhitequark2021-03-0710-0/+177
|\ | | | | sv: support for parameters without default values
| * sv: support for parameters without default valuesZachary Snow2021-03-0210-0/+177
| | | | | | | | | | | | | | | | | | - Modules with a parameter without a default value will be automatically deferred until the hierarchy pass - Allows for parameters without defaults as module items, rather than just int the `parameter_port_list`, despite being forbidden in the LRM - Check for parameters without defaults that haven't been overriden - Add location info to parameter/localparam declarations
* | Merge pull request #2632 from zachjs/width-limitwhitequark2021-03-072-0/+33
|\ \ | | | | | | verilog: impose limit on maximum expression width
| * | verilog: impose limit on maximum expression widthZachary Snow2021-03-042-0/+33
| |/ | | | | | | | | Designs with unreasonably wide expressions would previously get stuck allocating memory forever.
* / sv: fix some edge cases for unbased unsized literalsZachary Snow2021-03-062-0/+47
|/ | | | | | - Fix explicit size cast of unbased unsized literals - Fix unbased unsized literal bound directly to port - Output `is_unsized` flag in `dumpAst`
* verilog: fix sizing of ports with int types in module headersZachary Snow2021-03-012-0/+61
| | | | | | Declaring the ports as standard module items already worked as expected. This adds a missing usage of `checkRange()` so that headers such as `module m(output integer x);` now work correctly.
* verilog: fix handling of nested ifdef directivesZachary Snow2021-03-015-0/+50
| | | | | - track depth so we know whether to consider higher-level elsifs - error on unmatched endif/elsif/else
* Merge pull request #2615 from zachjs/genrtlil-conflictwhitequark2021-03-016-0/+56
|\ | | | | genrtlil: improve name conflict error messaging
| * genrtlil: improve name conflict error messagingZachary Snow2021-02-266-0/+56
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* | sv: extended support for integer typesZachary Snow2021-02-284-0/+78
|/ | | | | | | | | - Standard data declarations can now use any integer type - Parameters and localparams can now use any integer type - Function returns types can now use any integer type - Fix `parameter logic`, `localparam reg`, etc. to be 1 bit (previously 32 bits) - Added longint type (64 bits) - Unified parser source for integer type widths
* Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and ↵TimRudy2021-02-242-0/+438
| | | | turn-off (#2566)
* Merge pull request #2594 from zachjs/func-arg-widthwhitequark2021-02-234-0/+48
|\ | | | | verilog: fix sizing of constant args for tasks/functions
| * verilog: fix sizing of constant args for tasks/functionsZachary Snow2021-02-214-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases
* | verilog: error on macro invocations with missing argument listsZachary Snow2021-02-192-0/+22
|/ | | | | | This would previously complain about an undefined internal macro if the unapplied macro had not already been used. If it had, it would incorrectly use the arguments from the previous invocation.
* Merge pull request #2578 from zachjs/genblk-portZachary Snow2021-02-111-0/+12
|\ | | | | verlog: allow shadowing module ports within generate blocks
| * verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-071-0/+12
| | | | | | | | | | | | | | | | This is a somewhat obscure edge case I encountered while working on test cases for earlier changes. Declarations in generate blocks should not be checked against the list of ports. This change also adds a check forbidding declarations within generate blocks being tagged as inputs or outputs.
* | Add missing is_signed to type_atomKamil Rakoczy2021-02-111-0/+19
|/ | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Add check of begin/end labels for genblockKamil Rakoczy2021-02-041-0/+26
| | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: significant block scoping improvementsZachary Snow2021-01-319-0/+173
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* sv: fix support wire and var data type modifiersZachary Snow2021-01-202-0/+42
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* Merge pull request #2380 from Xiretza/parallel-testsclairexen2020-10-011-19/+3
|\ | | | | Clean up and parallelize testsuite
| * tests: Centralize test collection and Makefile generationXiretza2020-09-211-19/+3
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* | Update .gitignoreDavid Shah2020-10-011-0/+2
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | add testsN. Engelhardt2020-09-282-0/+49
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* Merge pull request #2080 from YosysHQ/eddie/fix_test_warningsEddie Hung2020-06-031-1/+1
|\ | | | | tests: reduce test warnings
| * tests: fix some test warningsEddie Hung2020-05-251-1/+1
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* | test: add attribute-before-stmt test from @nakengelhardtEddie Hung2020-05-251-0/+15
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* | verilog: do not warn for attributes on null statementsEddie Hung2020-05-251-4/+4
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* | tests: add an generate-else test tooEddie Hung2020-05-251-0/+34
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* | tests: add #2037 testcaseEddie Hung2020-05-251-0/+9
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* Merge pull request #2057 from YosysHQ/eddie/fix_task_attrEddie Hung2020-05-211-0/+28
|\ | | | | verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
| * tests: attributes before task enableEddie Hung2020-05-141-0/+28
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* Merge pull request #2045 from YosysHQ/eddie/fix2042Eddie Hung2020-05-144-0/+93
|\ | | | | verilog: error if no direction given for task arguments, default to input in SV mode
| * test: add another testcase as per @nakengelhardtEddie Hung2020-05-141-0/+25
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