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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 10:07:58 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 10:07:58 -0700 |
| commit | 60aa8049157eb4f0417022182aeb8c1581efe404 (patch) | |
| tree | c4c14d7ebe03463457e55491a570fb4e76dc13b7 /tests/verilog | |
| parent | ae11156c90eec958cd9ab631a28c41eccc105e56 (diff) | |
| download | yosys-60aa8049157eb4f0417022182aeb8c1581efe404.tar.gz yosys-60aa8049157eb4f0417022182aeb8c1581efe404.tar.bz2 yosys-60aa8049157eb4f0417022182aeb8c1581efe404.zip | |
tests: fix some test warnings
Diffstat (limited to 'tests/verilog')
| -rw-r--r-- | tests/verilog/bug2042-sv.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys index e815d7fc5..91989f412 100644 --- a/tests/verilog/bug2042-sv.ys +++ b/tests/verilog/bug2042-sv.ys @@ -2,7 +2,7 @@ read_verilog -sv <<EOT module Task_Test_Top ( input a, -output b +output reg b ); task SomeTaskName(a); |