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authorEddie Hung <eddie@fpgeh.com>2020-06-03 08:37:07 -0700
committerGitHub <noreply@github.com>2020-06-03 08:37:07 -0700
commit46ed0db2ec883a4ce330c81f321511e36e35c0b3 (patch)
treef4a5b3f6c72ffaa4a72b78a580c6d5949b62f37c /tests/verilog
parent577859fbdbefaabac4a3c61288264f2505261586 (diff)
parent60aa8049157eb4f0417022182aeb8c1581efe404 (diff)
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Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings
tests: reduce test warnings
Diffstat (limited to 'tests/verilog')
-rw-r--r--tests/verilog/bug2042-sv.ys2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys
index e815d7fc5..91989f412 100644
--- a/tests/verilog/bug2042-sv.ys
+++ b/tests/verilog/bug2042-sv.ys
@@ -2,7 +2,7 @@ read_verilog -sv <<EOT
module Task_Test_Top
(
input a,
-output b
+output reg b
);
task SomeTaskName(a);