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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-14 16:32:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 07:36:53 -0700 |
| commit | 95dcd7e785db44fd664fb7d5ac380fa642d0981c (patch) | |
| tree | 6b9a1319ee72d51c9ae2bab4b3a7a6e374e6447c /tests/verilog | |
| parent | 1c117ac0236517d0d7150dcc8d1fed19288bd692 (diff) | |
| download | yosys-95dcd7e785db44fd664fb7d5ac380fa642d0981c.tar.gz yosys-95dcd7e785db44fd664fb7d5ac380fa642d0981c.tar.bz2 yosys-95dcd7e785db44fd664fb7d5ac380fa642d0981c.zip | |
test: add attribute-before-stmt test from @nakengelhardt
Diffstat (limited to 'tests/verilog')
| -rw-r--r-- | tests/verilog/bug2037.ys | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/verilog/bug2037.ys b/tests/verilog/bug2037.ys index eb4f0fac4..4b629ba92 100644 --- a/tests/verilog/bug2037.ys +++ b/tests/verilog/bug2037.ys @@ -41,3 +41,18 @@ module test (); endmodule EOT select -assert-none a:* + + +design -reset +read_verilog <<EOT +module test (); + localparam y = 1; + reg x = 1'b0; + always @(*) begin + if (y) + (* foo *) x <= 1'b1; + else + (* bar *) x = 1'b0; + end +endmodule +EOT |