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* dffinit: Avoid setting init parameter to zero-length value.Marcelina Kościelnicka2020-04-141-0/+25
* zinit: resolve one more comment by @mwkmwkmwkEddie Hung2020-04-131-1/+8
* zinit: fix review comments from @mwkmwkmwkEddie Hung2020-04-131-4/+31
* tests: zinit on $adffEddie Hung2020-04-131-19/+18
* Add testcase for $_DFF_[NP][NP][01]_Eddie Hung2020-04-131-0/+24
* Merge pull request #1648 from YosysHQ/eddie/cmp2lcuEddie Hung2020-04-031-0/+52
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| * +/cmp2lcu.v to work efficiently for fully/partially constant inputsEddie Hung2020-04-031-3/+31
| * Refactor +/cmp2lcu.v into recursive techmapEddie Hung2020-04-031-1/+1
| * techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcuEddie Hung2020-04-031-0/+24
* | iopadmap: Fix z assignment to inout portMarcin Kościelnicki2020-04-021-1/+9
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* techmap: Fix cell names with _TECHMAP_REPLACE_.*Marcin Kościelnicki2020-03-231-0/+18
* iopadmap: Look harder for already-present buffers. (#1731)Marcelina Kościelnicka2020-03-021-2/+21
* Fine tune #1699 testsEddie Hung2020-02-131-14/+14
* iopadmap: move \init attributes from outpad output to its inputEddie Hung2020-02-131-0/+37
* shiftx2mux: fix select out of boundsEddie Hung2020-02-052-1/+12
* Merge remote-tracking branch 'origin/master' into eddie/shiftx2muxEddie Hung2020-02-051-0/+29
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| * Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-151-0/+13
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| * | abc9: respect (* keep *) on cellsEddie Hung2020-01-131-0/+15
| * | write_xaiger: add support and test for (* keep *) on wiresEddie Hung2020-01-131-0/+13
* | | Move from +/shiftx2mux.v into +/techmap.v; cleanupEddie Hung2020-01-211-4/+4
* | | New techmap +/shiftx2mux.v which decomposes LSB first; better for ABCEddie Hung2020-01-211-0/+110
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* | abc9: aAdd test to check $_NOT_s are absorbedEddie Hung2020-01-151-0/+12
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* Add abc9 sanity testEddie Hung2020-01-091-0/+40
* iopadmap: Emit tristate buffers with const OE for some edge cases.Marcin Kościelnicki2019-12-251-0/+23
* iopadmap: Refactor and fix tristate buffer mapping. (#1527)Marcin Kościelnicki2019-12-041-0/+99
* clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-5/+16
* Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-031-0/+10
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| * Add quick testEddie Hung2019-09-301-0/+10
* | Extend test with renaming cells with prefix tooEddie Hung2019-10-021-0/+2
* | Add testEddie Hung2019-09-301-0/+16
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* Fix _TECHMAP_REMOVEINIT_ handling.Marcin Kościelnicki2019-09-271-2/+12
* Hell let's add the original #1381 testcase tooEddie Hung2019-09-201-3/+22
* Add testcaseEddie Hung2019-09-201-0/+43
* Added extractinv passMarcin Kościelnicki2019-09-191-0/+41
* Add -match-init option to dff2dffs.Marcin Kościelnicki2019-09-111-0/+50
* techmap: Add support for extracting init values of portsMarcin Kościelnicki2019-09-071-0/+98
* improve clkbuf_inhibit propagation upwards through hierarchyMarcin Kościelnicki2019-08-271-5/+33
* Improve tests to check that clkbuf is connected to expectedEddie Hung2019-08-261-6/+21
* Check clkbuf_inhibit=1 is ignored for custom selectionEddie Hung2019-08-231-0/+1
* Add simple clkbufmap testsEddie Hung2019-08-231-0/+52
* tests/techmap/run-test.sh to cope with *.ysEddie Hung2019-08-232-7/+18
* Add testEddie Hung2019-08-203-0/+15
* Added read-enable to memory modelClifford Wolf2015-09-251-1/+8
* Added $meminit support to "memory" commandClifford Wolf2015-02-141-0/+5
* Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-161-2/+13
* Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.shClifford Wolf2014-03-111-1/+1
* Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)Clifford Wolf2014-03-111-1/+1
* Use private namespace in mem_simple_4x1_mapClifford Wolf2014-02-211-4/+4
* Added tests/techmap/mem_simple_4x1Clifford Wolf2014-02-217-0/+214
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