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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-04-14 16:33:09 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-04-14 19:52:19 +0200 |
commit | 7a36728b2fd640e166188b05c901b1992ec2af6b (patch) | |
tree | 6ffd51df2ce905caf597f945bd8addc3bd8320fe /tests/techmap | |
parent | 3a27906ac65a1287d1cc4ea758e639b608e152a6 (diff) | |
download | yosys-7a36728b2fd640e166188b05c901b1992ec2af6b.tar.gz yosys-7a36728b2fd640e166188b05c901b1992ec2af6b.tar.bz2 yosys-7a36728b2fd640e166188b05c901b1992ec2af6b.zip |
dffinit: Avoid setting init parameter to zero-length value.
Fixes #1704.
Diffstat (limited to 'tests/techmap')
-rw-r--r-- | tests/techmap/dffinit.ys | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/tests/techmap/dffinit.ys b/tests/techmap/dffinit.ys new file mode 100644 index 000000000..218d411f8 --- /dev/null +++ b/tests/techmap/dffinit.ys @@ -0,0 +1,25 @@ +read_verilog <<EOT + +module ff(...); +input d; +output q; + +endmodule + +module top(...); +input d; +output q1; +(* init = 1'b1 *) +output q2; + +ff my_ff1(.d(d), .q(q1)); +ff my_ff2(.d(d), .q(q2)); + +endmodule + +EOT + +dffinit -ff ff q init +select -assert-count 2 t:ff +select -assert-count 1 t:ff r:init %i +select -assert-count 1 t:ff r:init=1'b1 %i |