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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-13 19:07:55 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-13 19:07:55 -0800 |
| commit | 9ec948f3965eef214bee3af778b67fdd6ee86929 (patch) | |
| tree | dfe7b7b345876c0d172647a36ebaceeb752a2ae2 /tests/techmap | |
| parent | 0d2c06ee47a5008ba79d14d52f72d9b08ac2c7fc (diff) | |
| download | yosys-9ec948f3965eef214bee3af778b67fdd6ee86929.tar.gz yosys-9ec948f3965eef214bee3af778b67fdd6ee86929.tar.bz2 yosys-9ec948f3965eef214bee3af778b67fdd6ee86929.zip | |
write_xaiger: add support and test for (* keep *) on wires
Diffstat (limited to 'tests/techmap')
| -rw-r--r-- | tests/techmap/abc9.ys | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys index 20f263da8..46b6f08d2 100644 --- a/tests/techmap/abc9.ys +++ b/tests/techmap/abc9.ys @@ -38,3 +38,16 @@ abc9 -lut 4 design -load gold scratchpad -copy abc9.script.flow3 abc9.script abc9 -lut 4 + +design -reset +read_verilog <<EOT +module top(input a, b, output o); +(* keep *) wire w = a & b; +assign o = ~w; +endmodule +EOT + +simplemap +equiv_opt -assert abc9 -lut 4 +design -load postopt +select -assert-count 2 t:$lut |