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author | Clifford Wolf <clifford@clifford.at> | 2014-03-11 11:39:30 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-03-11 11:39:30 +0100 |
commit | 4fd1a4c12b8a57454bc6e7f3b7bba6a7aeade96c (patch) | |
tree | 05b0aa06aceb945e209adc497ca8c18174955747 /tests/techmap | |
parent | 78c64a64017dbc3e15aeac3246d5fc159555fbe2 (diff) | |
download | yosys-4fd1a4c12b8a57454bc6e7f3b7bba6a7aeade96c.tar.gz yosys-4fd1a4c12b8a57454bc6e7f3b7bba6a7aeade96c.tar.bz2 yosys-4fd1a4c12b8a57454bc6e7f3b7bba6a7aeade96c.zip |
Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)
Diffstat (limited to 'tests/techmap')
-rw-r--r-- | tests/techmap/mem_simple_4x1_runtest.sh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/techmap/mem_simple_4x1_runtest.sh b/tests/techmap/mem_simple_4x1_runtest.sh index 8285875b8..541da483e 100644 --- a/tests/techmap/mem_simple_4x1_runtest.sh +++ b/tests/techmap/mem_simple_4x1_runtest.sh @@ -2,7 +2,7 @@ set -ev -yosys -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v +yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v |