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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-09 18:17:06 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-09 18:17:06 -0800 |
| commit | a10016ccc57638aa837acd76fc93f296eda83b32 (patch) | |
| tree | e6c119e11b065a0523623e6cb532ea105b771394 /tests/techmap | |
| parent | e378902f939c24cb8f6cbff29c3f508a4655f3ab (diff) | |
| download | yosys-a10016ccc57638aa837acd76fc93f296eda83b32.tar.gz yosys-a10016ccc57638aa837acd76fc93f296eda83b32.tar.bz2 yosys-a10016ccc57638aa837acd76fc93f296eda83b32.zip | |
Add abc9 sanity test
Diffstat (limited to 'tests/techmap')
| -rw-r--r-- | tests/techmap/abc9.ys | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys new file mode 100644 index 000000000..20f263da8 --- /dev/null +++ b/tests/techmap/abc9.ys @@ -0,0 +1,40 @@ +read_verilog <<EOT +`define N 256 +module top(input [`N-1:0] a, output o); +wire [`N-2:0] w; +assign w[0] = a[0] & a[1]; +genvar i; +generate for (i = 1; i < `N-1; i++) +assign w[i] = w[i-1] & a[i+1]; +endgenerate +assign o = w[`N-2]; +endmodule +EOT +simplemap +dump +design -save gold + +abc9 -lut 4 + +design -load gold +abc9 -lut 4 -fast + +design -load gold +scratchpad -copy abc9.script.default.area abc9.script +abc9 -lut 4 + +design -load gold +scratchpad -copy abc9.script.default.fast abc9.script +abc9 -lut 4 + +design -load gold +scratchpad -copy abc9.script.flow abc9.script +abc9 -lut 4 + +design -load gold +scratchpad -copy abc9.script.flow2 abc9.script +abc9 -lut 4 + +design -load gold +scratchpad -copy abc9.script.flow3 abc9.script +abc9 -lut 4 |