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* Add retime testEddie Hung2019-04-051-0/+6
* fix local name resolution in prefix constructsZachary Snow2019-03-181-0/+56
* Fix handling of task output ports in clocked always blocks, fixes #857Clifford Wolf2019-03-071-0/+19
* Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v failsJim Lawson2019-03-041-0/+1
* Fix FIRRTL to Verilog process instance subfield assignment.Jim Lawson2019-02-251-1/+0
* Fix handling of defparam for when default_nettype is noneClifford Wolf2019-02-241-0/+2
* Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-171-0/+26
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| * Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-151-0/+26
* | Extend testcaseEddie Hung2019-02-061-2/+34
* | Add testcaseEddie Hung2019-02-061-0/+10
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* Basic test for checking correct synthesis of SystemVerilog interfacesRuben Undheim2018-10-181-90/+0
* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-3/+17
* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+76
* Fix tests/simple/specify.vClifford Wolf2018-03-271-2/+2
* First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-271-0/+31
* Allow $size and $bits in verilog mode, actually check test caseClifford Wolf2017-09-291-32/+0
* $size() now works correctly for all cases!Udi Finkelstein2017-09-261-5/+11
* $size() seems to work now with or without the optional parameter.Udi Finkelstein2017-09-261-8/+18
* Added $bits() for memories as well.Udi Finkelstein2017-09-261-6/+5
* $size() now works with memories as well!Udi Finkelstein2017-09-261-2/+4
* Add $size() function. At the moment it works only on expressions, not on memo...Udi Finkelstein2017-09-261-0/+15
* Squelch trailing whitespaceLarry Doolittle2017-04-121-1/+1
* Fixed typo in tests/simple/arraycells.vClifford Wolf2017-01-041-1/+1
* Added support for hierarchical defparamsClifford Wolf2016-11-151-0/+23
* Add optional SEED=n command line option to Makefile, and -S n command line op...Eric Smith2016-09-221-1/+12
* Fixed bug with memories that do not have a down-to-zero data widthClifford Wolf2016-08-221-0/+30
* Added another mem2reg test caseClifford Wolf2016-08-211-0/+11
* Another bugfix in mem2reg codeClifford Wolf2016-08-211-0/+22
* Fixed mem assignment in left-hand-side concatenationClifford Wolf2016-07-081-0/+13
* Fixed init issue in mem2reg_test2 test caseClifford Wolf2016-06-171-2/+6
* Added opt_expr support for div/mod by power-of-twoClifford Wolf2016-05-291-0/+27
* Bugfix and improvements in memory_shareClifford Wolf2016-04-211-0/+21
* Added tests/simple/graphtest.vClifford Wolf2015-11-301-0/+34
* More bugfixes in handling of parameters in tasks and functionsClifford Wolf2015-11-121-1/+12
* Fixed handling of parameters and localparams in functionsClifford Wolf2015-11-111-1/+30
* Bugfix in memory_dffClifford Wolf2015-10-311-0/+15
* Improvements in wreduceClifford Wolf2015-10-311-0/+9
* Another block of spelling fixesLarry Doolittle2015-08-144-6/+6
* Fixed trailing whitespacesClifford Wolf2015-07-023-6/+6
* Various fixes for memories with offsetsClifford Wolf2015-02-141-2/+2
* Added $meminit support to "memory" commandClifford Wolf2015-02-141-15/+8
* Added $meminit test caseClifford Wolf2015-02-141-0/+30
* improvements in muxtree/select_leaves testClifford Wolf2015-01-181-2/+5
* Improvements in opt_muxtreeClifford Wolf2015-01-181-0/+8
* Added support for task and function args in parenthesesClifford Wolf2014-10-271-1/+35
* Added multi-dim memory test (requires iverilog git head)Clifford Wolf2014-08-121-0/+11
* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-051-0/+63
* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-051-0/+13
* Added "make -j{N}" support to "make test"Clifford Wolf2014-07-301-1/+1
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-281-0/+57
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