iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fix "make vgtest" so it runs to the end (but now it fails ;)	Claire Xenia Wolf	2021-09-23	40	-79/+79
*	proc_rmdead: use explicit pattern set when there are no wildcards	Zachary Snow	2021-07-29	1	-0/+273
*	genrtlil: add width detection for AST_PREFIX nodes	Zachary Snow	2021-07-29	1	-0/+18
*	sv: fix up end label checking	Zachary Snow	2021-06-16	1	-0/+29
*	Merge pull request #2817 from YosysHQ/claire/fixemails	Claire Xen	2021-06-09	1	-1/+1
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\| *	More deadname stuff	Claire Xenia Wolf	2021-06-09	1	-1/+1
* \|	verilog: check for module scope identifiers during width detection	Zachary Snow	2021-06-08	1	-0/+11
* \|	mem2reg: tolerate out of bounds constant accesses	Zachary Snow	2021-06-08	1	-0/+19
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*	verilog: fix case expression sign and width handling	Zachary Snow	2021-05-25	2	-0/+108
*	sv: support remaining assignment operators	Zachary Snow	2021-05-25	1	-0/+23
*	verilog: fix buf/not primitives with multiple outputs	Xiretza	2021-03-17	1	-0/+15
*	verilog: support module scope identifiers in parametric modules	Zachary Snow	2021-03-16	1	-0/+29
*	verilog: fix handling of nested ifdef directives	Zachary Snow	2021-03-01	2	-0/+109
*	Merge pull request #2573 from zachjs/repeat-call	whitequark	2021-02-11	2	-0/+94
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\| *	verilog: refactored constant function evaluation	Zachary Snow	2021-02-04	2	-0/+94
* \|	verlog: allow shadowing module ports within generate blocks	Zachary Snow	2021-02-07	1	-0/+10
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*	Merge pull request #2529 from zachjs/unnamed-genblk	whitequark	2021-02-04	12	-0/+312
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\| *	verilog: significant block scoping improvements	Zachary Snow	2021-01-31	12	-0/+312
* \|	Merge pull request #2436 from dalance/fix_generate	whitequark	2021-02-03	2	-7/+4
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\| * \|	Fix begin/end in generate	dalance	2020-11-11	2	-7/+4
* \| \|	verilog: strip leading and trailing spaces in macro args	Zachary Snow	2021-01-28	1	-0/+20
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* \|	verilog: allow spaces in macro arguments	Zachary Snow	2021-01-20	1	-0/+28
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*	tests/simple: remove "nullglob" shopt	Xiretza	2020-09-21	1	-1/+0
*	Module name scope support	Zachary Snow	2020-08-20	1	-0/+16
*	Merge pull request #2339 from zachjs/display-format-0s	clairexen	2020-08-18	1	-0/+7
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\| *	Allow %0s $display format specifier	Zachary Snow	2020-08-09	1	-0/+7
* \|	Merge pull request #2338 from zachjs/const-branch-finish	clairexen	2020-08-18	1	-0/+39
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\| * \|	Propagate const_fold through generate blocks and branches	Zachary Snow	2020-08-09	1	-0/+39
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* /	Fix generate scoping issues	Zachary Snow	2020-07-31	1	-0/+85
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*	Expand tests/simple/constmuldivmod.v	Xiretza	2020-05-28	1	-1/+41
*	Bugfix in partsel.v signed indices test cases	Claire Wolf	2020-05-02	1	-2/+2
*	Add tests based on the test case from #1990	Claire Wolf	2020-05-02	1	-0/+46
*	Add dynamic slicing Verilog testcase	Eddie Hung	2020-03-31	1	-0/+12
*	Fix partsel expr bit width handling and add test case	Claire Wolf	2020-03-08	1	-0/+4
*	Make SV2017 compliant courtesy of @wsnyder	Eddie Hung	2019-12-12	1	-3/+1
*	simple/peepopt.v tests to various/peepopt.ys with equiv_opt & select	Eddie Hung	2019-09-05	1	-21/+0
*	Add peepopt_dffmuxext tests	Eddie Hung	2019-09-04	1	-0/+8
*	Use `command -v` rather than `which`	Emily	2019-09-03	1	-1/+1
*	Add test case for real parameters	Clifford Wolf	2019-08-20	1	-1/+10
*	Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog...	Jim Lawson	2019-07-31	1	-1/+3
*	Add test	Eddie Hung	2019-06-20	1	-0/+11
*	Add proper test for SV-style arrays	Clifford Wolf	2019-06-20	1	-0/+16
*	Add defvalue test, minor autotest fixes for .sv files	Clifford Wolf	2019-06-19	1	-0/+22
*	Rename implicit_ports.sv test to implicit_ports.v	Clifford Wolf	2019-06-07	1	-0/+0
*	Cleanup tux3-implicit_named_connection	Clifford Wolf	2019-06-07	1	-0/+16
*	Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...	Clifford Wolf	2019-06-07	1	-1/+2
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\| *	SystemVerilog support for implicit named port connections	tux3	2019-06-06	1	-1/+2
* \|	Added tests for attributes	Maciej Kurc	2019-06-03	9	-0/+219
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*	Merge pull request #1049 from YosysHQ/clifford/fix1047	Clifford Wolf	2019-05-28	1	-0/+4
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\| *	Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047	Clifford Wolf	2019-05-28	1	-0/+4