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* verilog: fix case expression sign and width handlingZachary Snow2021-05-252-0/+108
* sv: support remaining assignment operatorsZachary Snow2021-05-251-0/+23
* verilog: fix buf/not primitives with multiple outputsXiretza2021-03-171-0/+15
* verilog: support module scope identifiers in parametric modulesZachary Snow2021-03-161-0/+29
* verilog: fix handling of nested ifdef directivesZachary Snow2021-03-012-0/+109
* Merge pull request #2573 from zachjs/repeat-callwhitequark2021-02-112-0/+94
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| * verilog: refactored constant function evaluationZachary Snow2021-02-042-0/+94
* | verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-071-0/+10
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* Merge pull request #2529 from zachjs/unnamed-genblkwhitequark2021-02-0412-0/+312
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| * verilog: significant block scoping improvementsZachary Snow2021-01-3112-0/+312
* | Merge pull request #2436 from dalance/fix_generatewhitequark2021-02-032-7/+4
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| * | Fix begin/end in generatedalance2020-11-112-7/+4
* | | verilog: strip leading and trailing spaces in macro argsZachary Snow2021-01-281-0/+20
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* | verilog: allow spaces in macro argumentsZachary Snow2021-01-201-0/+28
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* tests/simple: remove "nullglob" shoptXiretza2020-09-211-1/+0
* Module name scope supportZachary Snow2020-08-201-0/+16
* Merge pull request #2339 from zachjs/display-format-0sclairexen2020-08-181-0/+7
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| * Allow %0s $display format specifierZachary Snow2020-08-091-0/+7
* | Merge pull request #2338 from zachjs/const-branch-finishclairexen2020-08-181-0/+39
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| * | Propagate const_fold through generate blocks and branchesZachary Snow2020-08-091-0/+39
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* / Fix generate scoping issuesZachary Snow2020-07-311-0/+85
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* Expand tests/simple/constmuldivmod.vXiretza2020-05-281-1/+41
* Bugfix in partsel.v signed indices test casesClaire Wolf2020-05-021-2/+2
* Add tests based on the test case from #1990Claire Wolf2020-05-021-0/+46
* Add dynamic slicing Verilog testcaseEddie Hung2020-03-311-0/+12
* Fix partsel expr bit width handling and add test caseClaire Wolf2020-03-081-0/+4
* Make SV2017 compliant courtesy of @wsnyderEddie Hung2019-12-121-3/+1
* simple/peepopt.v tests to various/peepopt.ys with equiv_opt & selectEddie Hung2019-09-051-21/+0
* Add peepopt_dffmuxext testsEddie Hung2019-09-041-0/+8
* Use `command -v` rather than `which`Emily2019-09-031-1/+1
* Add test case for real parametersClifford Wolf2019-08-201-1/+10
* Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog...Jim Lawson2019-07-311-1/+3
* Add testEddie Hung2019-06-201-0/+11
* Add proper test for SV-style arraysClifford Wolf2019-06-201-0/+16
* Add defvalue test, minor autotest fixes for .sv filesClifford Wolf2019-06-191-0/+22
* Rename implicit_ports.sv test to implicit_ports.vClifford Wolf2019-06-071-0/+0
* Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-071-0/+16
* Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...Clifford Wolf2019-06-071-1/+2
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| * SystemVerilog support for implicit named port connectionstux32019-06-061-1/+2
* | Added tests for attributesMaciej Kurc2019-06-039-0/+219
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* Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-281-0/+4
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| * Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-281-0/+4
* | Add actual wandwor test that is part of "make test"Clifford Wolf2019-05-281-0/+36
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* Added tests for Verilog frontent for attributes on parameters and localparamsMaciej Kurc2019-05-162-0/+22
* Add test case from #997Clifford Wolf2019-05-071-0/+12
* Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-063-0/+32
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| * Merge pull request #969 from YosysHQ/clifford/pmgenstuffClifford Wolf2019-05-031-0/+9
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| | * Add peepopt_muldiv, fixes #930Clifford Wolf2019-04-301-0/+9
| * | Merge pull request #976 from YosysHQ/clifford/fix974Clifford Wolf2019-05-031-0/+22
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| | * | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+22
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