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* synth_xilinx: Use opt_dff.Marcelina Kościelnicka2020-07-301-9/+7
| | | | | | | | | The main part is converting xilinx_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* intel_alm: direct M10K instantiationDan Ravensloft2020-07-271-0/+6
| | | | This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
* intel_alm: increase abc9 -WDan Ravensloft2020-07-261-6/+6
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* satgen: Add support for dffe, sdff, sdffe, sdffce cells.Marcelina Kościelnicka2020-07-241-2/+0
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* intel_alm: add additional ABC9 timingsDan Ravensloft2020-07-231-6/+4
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* Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogicMiodrag Milanović2020-07-161-12/+14
|\ | | | | anlogic: Use dfflegalize.
| * anlogic: Use dfflegalize.Marcelina Kościelnicka2020-07-141-12/+14
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* | Revert "intel_alm: direct M10K instantiation"Lofty2020-07-131-6/+0
| | | | | | | | This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
* | xilinx: Fix srl regression.Marcelina Kościelnicka2020-07-121-0/+41
| | | | | | | | | | | | | | Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and $_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the point where xilinx_srl is called for non-abc9. Fix this by running ff_map.v first, resulting in FDRE cells, which are handled correctly.
* | gowin: Use dfflegalize.Marcelina Kościelnicka2020-07-062-13/+8
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* | intel_alm: direct M10K instantiationDan Ravensloft2020-07-051-0/+6
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* | synth_gowin: ABC9 supportDan Ravensloft2020-07-051-1/+5
| | | | | | | | | | This adds ABC9 support for synth_gowin; drastically improving synthesis quality.
* | intel_alm: add Cyclone 10 GX testsDan Ravensloft2020-07-0511-2/+236
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* | intel_alm: DSP inferenceDan Ravensloft2020-07-051-0/+23
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* | synth_intel_alm: Use dfflegalize.Marcelina Kościelnicka2020-07-041-1/+1
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* | Improve MISTRAL_FF specify rulesDan Ravensloft2020-07-041-1/+2
| | | | | | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* | tests: update fsm.ys resource countEddie Hung2020-07-041-4/+4
|/ | | | | Suspect it is to do with map/set ordering in techmap; should be fixed by #1862?
* intel_alm: fix DFFE matchingDan Ravensloft2020-06-112-4/+4
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* Add missing .gitignore fileClaire Wolf2020-06-041-0/+2
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improveEddie Hung2020-06-041-4/+53
|\ | | | | abc9: -dff improvements
| * abc9_ops: update messaging (credit to @Xiretza for spotting)Eddie Hung2020-05-301-4/+4
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| * tests: add test for abc9 -dff removing a redundant flop entirelyEddie Hung2020-05-251-0/+15
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| * tests: add testcase for abc9 -dff preserving flop namesEddie Hung2020-05-251-0/+34
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* | Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixesEddie Hung2020-06-031-0/+13
|\ \ | | | | | | abc9: fixes around handling combinatorial loops
| * | tests: tidy up testcaseEddie Hung2020-06-031-3/+0
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| * | tests: add ecp5 latch testcase with -abc9Eddie Hung2020-05-251-0/+16
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* | | Merge pull request #2080 from YosysHQ/eddie/fix_test_warningsEddie Hung2020-06-032-2/+2
|\ \ \ | | | | | | | | tests: reduce test warnings
| * | | tests: fix some test warningsEddie Hung2020-05-252-2/+2
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* | | allow range for mux testMiodrag Milanovic2020-06-011-1/+2
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* | tests: xilinx macc test to have initval, shorten BMC depth for runtimeEddie Hung2020-05-252-8/+8
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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-191-2/+4
| | | | Fixes #2058.
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-5/+29
| | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
* abc9: suppress warnings when no compatible + used flop boxes formedEddie Hung2020-05-141-1/+3
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* xilinx: update abc9_dff testsEddie Hung2020-05-141-18/+45
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* xilinx: remove no-longer-relevant testEddie Hung2020-05-141-91/+0
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* intel_alm: direct LUTRAM cell instantiationDan Ravensloft2020-05-071-0/+20
| | | | | | | | | | By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus.
* intel_alm: work around a Quartus ICEDan Ravensloft2020-04-231-0/+12
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* tests: read +/xilinx/cell_sim.v before xilinx_dsp testEddie Hung2020-04-221-0/+1
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* test: ice40_dsp test to read +/ice40/cells_sim.v for default paramsEddie Hung2020-04-221-0/+1
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* xilinx: xilinx_dffopt to read cells_sim.v; fix testEddie Hung2020-04-221-13/+22
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* tests: remove write_ilangEddie Hung2020-04-202-3/+0
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* synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-1510-0/+208
| | | | | | | | By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-105-35/+551
|\ | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * ecp5: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-16/+62
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| * ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-8/+28
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| * ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-063-5/+305
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
| * ice40: match memory inference attribute values case insensitive.whitequark2020-02-061-0/+6
| | | | | | | | LSE/Synplify use case insensitive matching.
| * ice40: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-063-20/+179
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify appear to interpret attribute values insensitive to case. There is currently no way to do this in Yosys (attrmap can only change case of attribute names). * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
| * ice40: remove impossible test.whitequark2020-02-061-15/+0
| | | | | | | | | | | | iCE40 does not have LUTRAM. This was erroneously added in commit caab66111e2b5052bd26c8fd64b1324e7e4a4106, and tested for BRAM, essentially a duplicate of the "dpram.ys" test.
* | Merge pull request #1790 from YosysHQ/eddie/opt_expr_xorEddie Hung2020-04-012-7/+3
|\ \ | | | | | | opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
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