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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-30 08:57:48 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-30 08:57:48 -0700 |
| commit | ea4374a2239e3975a7451b083e5756139596a02e (patch) | |
| tree | dc00d9aee2c111dd68be1b4cc4ea9056873cf1e6 /tests/arch | |
| parent | b17e8495b83bc8fa13a5ac982b44c0b68d71a68a (diff) | |
| download | yosys-ea4374a2239e3975a7451b083e5756139596a02e.tar.gz yosys-ea4374a2239e3975a7451b083e5756139596a02e.tar.bz2 yosys-ea4374a2239e3975a7451b083e5756139596a02e.zip | |
abc9_ops: update messaging (credit to @Xiretza for spotting)
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/xilinx/abc9_dff.ys | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys index e3889be05..210e87477 100644 --- a/tests/arch/xilinx/abc9_dff.ys +++ b/tests/arch/xilinx/abc9_dff.ys @@ -50,10 +50,10 @@ FDCE_1 /*#(.INIT(1))*/ fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6])); FDPE_1 #(.INIT(1)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7])); endmodule EOT -logger -expect warning "Module '\$paramod\\FDRE\\INIT=1' contains a \$dff cell .*" 1 -logger -expect warning "Module '\$paramod\\FDRE_1\\INIT=1' contains a \$dff cell .*" 1 -logger -expect warning "Module 'FDSE' contains a \$dff cell .*" 1 -logger -expect warning "Module '\$paramod\\FDSE_1\\INIT=1' contains a \$dff cell .*" 1 +logger -expect warning "Whitebox '\$paramod\\FDRE\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1 +logger -expect warning "Whitebox '\$paramod\\FDRE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1 +logger -expect warning "Whitebox 'FDSE' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1 +logger -expect warning "Whitebox '\$paramod\\FDSE_1\\INIT=1' with \(\* abc9_flop \*\) contains a \$dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox\." 1 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf design -load postopt select -assert-count 8 t:FD* |