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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 10:07:58 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 10:07:58 -0700 |
| commit | 60aa8049157eb4f0417022182aeb8c1581efe404 (patch) | |
| tree | c4c14d7ebe03463457e55491a570fb4e76dc13b7 /tests/arch | |
| parent | ae11156c90eec958cd9ab631a28c41eccc105e56 (diff) | |
| download | yosys-60aa8049157eb4f0417022182aeb8c1581efe404.tar.gz yosys-60aa8049157eb4f0417022182aeb8c1581efe404.tar.bz2 yosys-60aa8049157eb4f0417022182aeb8c1581efe404.zip | |
tests: fix some test warnings
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/xilinx/pmgen_xilinx_srl.ys | 2 | ||||
| -rw-r--r-- | tests/arch/xilinx/xilinx_srl.v | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/tests/arch/xilinx/pmgen_xilinx_srl.ys b/tests/arch/xilinx/pmgen_xilinx_srl.ys index ea2f20487..e76fb20ab 100644 --- a/tests/arch/xilinx/pmgen_xilinx_srl.ys +++ b/tests/arch/xilinx/pmgen_xilinx_srl.ys @@ -1,6 +1,6 @@ read_verilog -icells <<EOT module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO); - parameter DEPTH = 1; + parameter DEPTH = 2; parameter [DEPTH-1:0] INIT = 0; parameter CLKPOL = 1; parameter ENPOL = 2; diff --git a/tests/arch/xilinx/xilinx_srl.v b/tests/arch/xilinx/xilinx_srl.v index bc2a15ab2..29920da41 100644 --- a/tests/arch/xilinx/xilinx_srl.v +++ b/tests/arch/xilinx/xilinx_srl.v @@ -29,7 +29,7 @@ endmodule module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q); parameter CLKPOL = 1; parameter ENPOL = 1; -parameter DEPTH = 1; +parameter DEPTH = 2; parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; reg [DEPTH-1:0] r = INIT; wire clk = C ^ CLKPOL; |