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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-04-25 17:25:59 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-05 05:39:20 +0200 |
| commit | b004f0901873962ba4a6fd3e12c7bc0cc1e04032 (patch) | |
| tree | 16d1bceb58a8b58690b5ba849173bfeef015bd4e /tests/arch | |
| parent | 01772dec8c13fb331df439319f4619b6292d6409 (diff) | |
| download | yosys-b004f0901873962ba4a6fd3e12c7bc0cc1e04032.tar.gz yosys-b004f0901873962ba4a6fd3e12c7bc0cc1e04032.tar.bz2 yosys-b004f0901873962ba4a6fd3e12c7bc0cc1e04032.zip | |
intel_alm: DSP inference
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/intel_alm/mul.ys | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/tests/arch/intel_alm/mul.ys b/tests/arch/intel_alm/mul.ys new file mode 100644 index 000000000..92f00156a --- /dev/null +++ b/tests/arch/intel_alm/mul.ys @@ -0,0 +1,23 @@ +read_verilog ../common/mul.v +hierarchy -top top +proc +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclonev # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +stat + +select -assert-count 1 t:MISTRAL_MUL9X9 +select -assert-none t:MISTRAL_MUL9X9 %% t:* %D + +design -reset +read_verilog ../common/mul.v +hierarchy -top top +proc +equiv_opt -assert -map +/intel_alm/common/dsp_sim.v synth_intel_alm -family cyclone10gx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +# Cyclone 10 GX does not have 9x9 multipliers, so we use 18x18. +select -assert-count 1 t:MISTRAL_MUL18X18 +select -assert-none t:MISTRAL_MUL18X18 %% t:* %D |